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Class Information
Number: 365/155
Name: Static information storage and retrieval > Systems using particular element > Flip-flop (electrical) > Plural emitter or collector
Description: Subject matter in which the flip-flop is made up of solid-state devices which have plural emitters or plural collectors.

Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8638592 Dual port static random access memory cell Jan. 28, 2014
8531872 Semiconductor integrated circuit and manufacturing method thereof Sep. 10, 2013
8526218 Memory design Sep. 3, 2013
8456885 Random access memory circuit Jun. 4, 2013
8405159 Semiconductor device Mar. 26, 2013
8391059 Methods for operating a semiconductor device Mar. 5, 2013
8213226 Vertical transistor memory cell and array Jul. 3, 2012
8107279 Semiconductor integrated circuit and manufacturing method therefor Jan. 31, 2012
7903450 Asymmetrical memory cells and memories using the cells Mar. 8, 2011
7898848 Memory including bipolar junction transistor select devices Mar. 1, 2011
7755927 Memory device of SRAM type Jul. 13, 2010
7742327 Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell Jun. 22, 2010
7738274 Content-addressable memory architecture Jun. 15, 2010
7719880 Method and system for semiconductor memory May. 18, 2010
7706172 Layout of a SRAM memory cell Apr. 27, 2010
7684263 Method and circuit for implementing enhanced SRAM write and read performance ring oscillator Mar. 23, 2010
7643329 Asymmetric four-transistor SRAM cell Jan. 5, 2010
7606060 Eight transistor SRAM cell with improved stability requiring only one word line Oct. 20, 2009
7596013 Semiconductor integrated circuit and manufacturing method therefor Sep. 29, 2009
7532539 Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load May. 12, 2009
7492628 Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell Feb. 17, 2009
7443715 SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Oct. 28, 2008
7443717 Semiconductor device Oct. 28, 2008
7382678 Delay stage-interweaved analog DLL/PLL Jun. 3, 2008
7362606 Asymmetrical memory cells and memories using the cells Apr. 22, 2008
7313012 Back-gate controlled asymmetrical memory cell and memory using the cell Dec. 25, 2007
7295458 Eight transistor SRAM cell with improved stability requiring only one word line Nov. 13, 2007
7242607 Diode-based memory including floating-plate capacitor and its applications Jul. 10, 2007
7139190 Single event upset tolerant memory cell layout Nov. 21, 2006
6914804 Memory cells enhanced for resistance to single event upset Jul. 5, 2005
6859387 Three-state binary adders and methods of operating the same Feb. 22, 2005
6735110 Memory cells enhanced for resistance to single event upset May. 11, 2004
6618283 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal Sep. 9, 2003
6529401 Semiconductor memory Mar. 4, 2003
6271568 Voltage controlled resistance modulation for single event upset immunity Aug. 7, 2001
6096496 Supports incorporating vertical cavity emitting lasers and tracking apparatus for use in combinatorial synthesis Aug. 1, 2000
6088259 SRAM cell using two single transistor inverters Jul. 11, 2000
5966324 Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells Oct. 12, 1999
5661681 Semiconductor memory and method of writing, reading, and sustaining data thereof Aug. 26, 1997
5383153 Semiconductor memory device with flash-clear function Jan. 17, 1995
5289409 Bipolar transistor memory cell and method Feb. 22, 1994
5276638 Bipolar memory cell with isolated PNP load Jan. 4, 1994
5216630 Static semiconductor memory device using bipolar transistor Jun. 1, 1993
5200924 Bit line discharge and sense circuit Apr. 6, 1993
5140399 Heterojunction bipolar transistor and the manufacturing method thereof Aug. 18, 1992
5117390 Semiconductor memory system for use in logic LSI's May. 26, 1992
5117391 Bipolar memory cell array biasing technique with forward active PNP load cell May. 26, 1992
5091881 Multiple port memory including merged bipolar transistors Feb. 25, 1992
5083292 Bipolar random access memory Jan. 21, 1992
5043939 Soft error immune memory Aug. 27, 1991

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