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Class Information
Number: 365/155
Name: Static information storage and retrieval > Systems using particular element > Flip-flop (electrical) > Plural emitter or collector
Description: Subject matter in which the flip-flop is made up of solid-state devices which have plural emitters or plural collectors.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7606060 |
Eight transistor SRAM cell with improved stability requiring only one word line |
Oct. 20, 2009 |
| 7596013 |
Semiconductor integrated circuit and manufacturing method therefor |
Sep. 29, 2009 |
| 7532539 |
Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load |
May. 12, 2009 |
| 7492628 |
Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell |
Feb. 17, 2009 |
| 7443715 |
SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
Oct. 28, 2008 |
| 7443717 |
Semiconductor device |
Oct. 28, 2008 |
| 7382678 |
Delay stage-interweaved analog DLL/PLL |
Jun. 3, 2008 |
| 7362606 |
Asymmetrical memory cells and memories using the cells |
Apr. 22, 2008 |
| 7313012 |
Back-gate controlled asymmetrical memory cell and memory using the cell |
Dec. 25, 2007 |
| 7295458 |
Eight transistor SRAM cell with improved stability requiring only one word line |
Nov. 13, 2007 |
| 7242607 |
Diode-based memory including floating-plate capacitor and its applications |
Jul. 10, 2007 |
| 7139190 |
Single event upset tolerant memory cell layout |
Nov. 21, 2006 |
| 6914804 |
Memory cells enhanced for resistance to single event upset |
Jul. 5, 2005 |
| 6859387 |
Three-state binary adders and methods of operating the same |
Feb. 22, 2005 |
| 6735110 |
Memory cells enhanced for resistance to single event upset |
May. 11, 2004 |
| 6618283 |
System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal |
Sep. 9, 2003 |
| 6529401 |
Semiconductor memory |
Mar. 4, 2003 |
| 6271568 |
Voltage controlled resistance modulation for single event upset immunity |
Aug. 7, 2001 |
| 6096496 |
Supports incorporating vertical cavity emitting lasers and tracking apparatus for use in combinatorial synthesis |
Aug. 1, 2000 |
| 6088259 |
SRAM cell using two single transistor inverters |
Jul. 11, 2000 |
| 5966324 |
Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells |
Oct. 12, 1999 |
| 5661681 |
Semiconductor memory and method of writing, reading, and sustaining data thereof |
Aug. 26, 1997 |
| 5383153 |
Semiconductor memory device with flash-clear function |
Jan. 17, 1995 |
| 5289409 |
Bipolar transistor memory cell and method |
Feb. 22, 1994 |
| 5276638 |
Bipolar memory cell with isolated PNP load |
Jan. 4, 1994 |
| 5216630 |
Static semiconductor memory device using bipolar transistor |
Jun. 1, 1993 |
| 5200924 |
Bit line discharge and sense circuit |
Apr. 6, 1993 |
| 5140399 |
Heterojunction bipolar transistor and the manufacturing method thereof |
Aug. 18, 1992 |
| 5117390 |
Semiconductor memory system for use in logic LSI's |
May. 26, 1992 |
| 5117391 |
Bipolar memory cell array biasing technique with forward active PNP load cell |
May. 26, 1992 |
| 5091881 |
Multiple port memory including merged bipolar transistors |
Feb. 25, 1992 |
| 5083292 |
Bipolar random access memory |
Jan. 21, 1992 |
| 5043939 |
Soft error immune memory |
Aug. 27, 1991 |
| 5029127 |
Bipolar SRAM having word lines as vertically stacked pairs of conductive lines parallelly formed with holding current lines |
Jul. 2, 1991 |
| 5029129 |
High-speed bipolar memory system |
Jul. 2, 1991 |
| 5023835 |
Semiconductor memory system for use in logic LSI's |
Jun. 11, 1991 |
| 5016214 |
Memory cell with separate read and write paths and clamping transistors |
May. 14, 1991 |
| 4956688 |
Radiation resistant bipolar memory |
Sep. 11, 1990 |
| 4922411 |
Memory cell circuit with supplemental current |
May. 1, 1990 |
| 4899311 |
Clamping sense amplifier for bipolar ram |
Feb. 6, 1990 |
| 4868904 |
Complementary noise-immune logic |
Sep. 19, 1989 |
| 4866673 |
BI-MOS semiconductor memory having high soft error immunity |
Sep. 12, 1989 |
| 4864540 |
Bipolar ram having no write recovery time |
Sep. 5, 1989 |
| 4864539 |
Radiation hardened bipolar static RAM cell |
Sep. 5, 1989 |
| 4858181 |
Fast recovery PNP loaded bipolar static RAM memory cell with an independent current path |
Aug. 15, 1989 |
| 4853898 |
Bipolar ram having state dependent write current |
Aug. 1, 1989 |
| 4823315 |
Plural emitter memory with voltage clamping plural emitter transistor |
Apr. 18, 1989 |
| 4809052 |
Semiconductor memory device |
Feb. 28, 1989 |
| 4805149 |
Digital memory with reset/preset capabilities |
Feb. 14, 1989 |
| 4792923 |
Bipolar semiconductor memory device with double word lines structure |
Dec. 20, 1988 |
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