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Class Information
Number: 345/570
Name: Computer graphics processing, operator interface processing, and selective visual display systems > Computer graphics display memory system > Addressing > Page mode
Description: Subject matter including accessing sequential memory locations in the graphics display memory with reduced cycle time.










Patents under this class:

Patent Number Title Of Patent Date Issued
8654136 Memory paging system for real time motion data recording, editing, and playback Feb. 18, 2014
8493396 Multidimensional datapath processing in a video processor Jul. 23, 2013
8296388 Cross-application encoding of geographical location information Oct. 23, 2012
8274521 System available cache color map Sep. 25, 2012
7859541 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation Dec. 28, 2010
7620793 Mapping memory partitions to virtual memory pages Nov. 17, 2009
7562184 DRAM controller for graphics processing operable to enable/disable burst transfer Jul. 14, 2009
7545382 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation Jun. 9, 2009
7102646 Demand-based memory system for graphics applications Sep. 5, 2006
7047373 Memory control apparatus and method for controlling memory access capable of selecting desirable page mode May. 16, 2006
6847370 Planar byte memory organization with linear access Jan. 25, 2005
6833834 Frame buffer organization and reordering Dec. 21, 2004
6680737 Z test and conditional merger of colliding pixels during batch building Jan. 20, 2004
6633298 Creating column coherency for burst building in a memory access command stream Oct. 14, 2003
6628292 Creating page coherency and improved bank sequencing in a memory access command stream Sep. 30, 2003
6559852 Z test and conditional merger of colliding pixels during batch building May. 6, 2003
6542159 Apparatus to control memory accesses in a video system and method thereof Apr. 1, 2003
6295074 Data processing apparatus having DRAM incorporated therein Sep. 25, 2001
6249853 GART and PTES defined by configuration registers Jun. 19, 2001
6091428 Frame buffer memory system for reducing page misses when rendering with color and Z buffers Jul. 18, 2000
6078336 Graphics memory system that utilizes look-ahead paging for reducing paging overhead Jun. 20, 2000
6052134 Memory controller and method for dynamic page management Apr. 18, 2000
6018354 Method for accessing banks of DRAM Jan. 25, 2000
5982398 Image processing device Nov. 9, 1999
5852451 Pixel reordering for improved texture mapping Dec. 22, 1998
5796412 Image data storing method and processing apparatus thereof Aug. 18, 1998
5687357 Register array for utilizing burst mode transfer on local bus Nov. 11, 1997
5642138 Display control system using a different clock in the graphics mode from that in the text mode in accessing an image memory Jun. 24, 1997
5612863 Sorting sequential data prior to distribution over parallel processors in random access manner Mar. 18, 1997
5577193 Multiple data registers and addressing technique therefore for block/flash writing main memory of a DRAM/VRAM Nov. 19, 1996
5559952 Display controller incorporating cache memory dedicated for VRAM Sep. 24, 1996
5412777 Display device having a built-in memory May. 2, 1995
5353402 Computer graphics display system having combined bus and priority reading of video memory Oct. 4, 1994
5321809 Categorized pixel variable buffering and processing for a graphics system Jun. 14, 1994
5233689 Methods and apparatus for maximizing column address coherency for serial and random port accesses to a dual port RAM array Aug. 3, 1993
4983958 Vector selectable coordinate-addressable DRAM array Jan. 8, 1991
4800380 Multi-plane page mode video memory controller Jan. 24, 1989
4766431 Peripheral apparatus for image memories Aug. 23, 1988











 
 
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