| |
 |
|
Class Information
Number: 341/113
Name: Coded data generation or conversion > Phase or time of phase change > Synchro or resolver signal > Coarse and fine
Description: Subject matter comprising two or more distinct and related conversions one of which has an output comprising the more significant bits of the digital signal and the other of which has an output comprising the less significant bits of the digital signal.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7835463 |
Digital radio frequency memory |
Nov. 16, 2010 |
| 7821431 |
Universal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters |
Oct. 26, 2010 |
| 7539276 |
Method of processing a sampled spread spectrum signal stream |
May. 26, 2009 |
| 7268710 |
Logic device for the transformation of the output of the RDC into series A-B pulses |
Sep. 11, 2007 |
| 7215142 |
Multi-stage inverse toggle |
May. 8, 2007 |
| 7084790 |
Device to effectuate a digital estimate of a periodic electric signal, related method and control system for an electric motor which comprises said device |
Aug. 1, 2006 |
| 6778119 |
Method and apparatus for accurate digital-to-analog conversion |
Aug. 17, 2004 |
| 6535152 |
Analog-to-digital converter having gamma-corrected reference voltages |
Mar. 18, 2003 |
| 6166573 |
High resolution delay line |
Dec. 26, 2000 |
| 5191336 |
Digital time interpolation system |
Mar. 2, 1993 |
| 5121116 |
Absolute position encoder |
Jun. 9, 1992 |
| 5008670 |
Phase/digital conversion method and arrangements for implementing the method |
Apr. 16, 1991 |
| 4992716 |
Motor control with digital feedback |
Feb. 12, 1991 |
| 4340939 |
Solid-state resolver apparatus including digital angle modifier |
Jul. 20, 1982 |
| 4308525 |
Dual speed resolver to digital converter with improved course-fine interlock |
Dec. 29, 1981 |
| 4014014 |
Synchronized multispeed transducer position indicating system |
Mar. 22, 1977 |
|
|
|
