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Class Information
Number: 327/415
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Gating (i.e., switching input to output) > Diverging with single input and plural outputs
Description: Subject matter comprising at least two signal paths having a single input and separate outputs, each signal path containing at least one switch.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7626421 |
Interface circuit and electronic device |
Dec. 1, 2009 |
| 7605726 |
Circuit and method for data alignment |
Oct. 20, 2009 |
| 7579896 |
Method and apparatus for generating multiple analog signals using a single microcontroller output pin |
Aug. 25, 2009 |
| 7554355 |
Crossbar switch architecture for multi-processor SoC platform |
Jun. 30, 2009 |
| 7482844 |
Analog-to-digital converter with programmable floating gate |
Jan. 27, 2009 |
| 7479825 |
Clock forming method for semiconductor integrated circuit and program product for the method |
Jan. 20, 2009 |
| 7477176 |
Method and apparatus for generating multiple analog signals using a single microcontroller output pin |
Jan. 13, 2009 |
| 7463080 |
Methods and systems for converting a single-ended signal to a differential signal |
Dec. 9, 2008 |
| 7460565 |
Data communications circuit with multi-stage multiplexing |
Dec. 2, 2008 |
| 7365578 |
Semiconductor device with pump circuit |
Apr. 29, 2008 |
| 7355534 |
Serial-to-parallel conversion circuit, and semiconductor display device employing the same |
Apr. 8, 2008 |
| 7292498 |
Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices |
Nov. 6, 2007 |
| 7148737 |
Semiconductor switching circuit |
Dec. 12, 2006 |
| 7119602 |
Low-skew single-ended to differential converter |
Oct. 10, 2006 |
| 6897688 |
Input/output buffer having analog and digital input modes |
May. 24, 2005 |
| 6891426 |
Circuit for providing multiple voltage signals |
May. 10, 2005 |
| 6750792 |
Serial-to-parallel conversion circuit, and semiconductor display device employing the same |
Jun. 15, 2004 |
| 6583659 |
Reduced clock-skew in a multi-output clock driver by selective shorting together of clock pre-outputs |
Jun. 24, 2003 |
| 6580313 |
System and method for providing single pin bypass for multiple circuits |
Jun. 17, 2003 |
| 6566890 |
Circuit for improved test and calibration in automated test equipment |
May. 20, 2003 |
| 6545524 |
Configurable multiplexing circuit and method |
Apr. 8, 2003 |
| 6535049 |
Multipurpose test chip input/output circuit |
Mar. 18, 2003 |
| 6483888 |
Clock divider with bypass and stop clock |
Nov. 19, 2002 |
| 6420981 |
Oversampling circuit and method |
Jul. 16, 2002 |
| 6414528 |
Clock generation circuit, serial/parallel conversion device and parallel/serial conversion device together with semiconductor device |
Jul. 2, 2002 |
| 6407613 |
Multipurpose test chip input/output circuit |
Jun. 18, 2002 |
| 6407614 |
Semiconductor integrated switching circuit |
Jun. 18, 2002 |
| 6380785 |
Method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations |
Apr. 30, 2002 |
| 6351175 |
Mode select circuit |
Feb. 26, 2002 |
| 6323716 |
Signal distributing circuit and signal line connecting method |
Nov. 27, 2001 |
| 6285237 |
Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice |
Sep. 4, 2001 |
| 6255884 |
Uniform clock timing circuit |
Jul. 3, 2001 |
| 6208186 |
Differential signal generator |
Mar. 27, 2001 |
| 6087887 |
Signal routing circuits having selective high impedance and low impedance output states |
Jul. 11, 2000 |
| 5995016 |
Method and apparatus for N choose M device selection |
Nov. 30, 1999 |
| 5994948 |
CMOS twin-tub negative voltage switching architecture |
Nov. 30, 1999 |
| 5917362 |
Switching circuit |
Jun. 29, 1999 |
| 5917363 |
Multiplexed driver system requiring a reduced number of amplifier circuits |
Jun. 29, 1999 |
| 5917364 |
Bi-directional interface circuit of reduced signal alteration |
Jun. 29, 1999 |
| 5910747 |
Method for optimization of multi-level interconnect RC delay |
Jun. 8, 1999 |
| 5905401 |
Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice |
May. 18, 1999 |
| 5894176 |
Flexible reset scheme supporting normal system operation, test and emulation modes |
Apr. 13, 1999 |
| 5886562 |
Method and apparatus for synchronizing a plurality of output clock signals generated from a clock input signal |
Mar. 23, 1999 |
| 5874790 |
Method and apparatus for a plurality of modules to independently read a single sensor |
Feb. 23, 1999 |
| 5856754 |
Semiconductor integrated circuit with parallel/serial/parallel conversion |
Jan. 5, 1999 |
| 5742182 |
Symmetric selector circuit for event logic |
Apr. 21, 1998 |
| 5736889 |
Duplexing control apparatus for use in a time division switching device |
Apr. 7, 1998 |
| 5726990 |
Multiplexer and demultiplexer |
Mar. 10, 1998 |
| 5675584 |
High speed serial link for fully duplexed data communication |
Oct. 7, 1997 |
| 5640117 |
Digital signal transmission circuit |
Jun. 17, 1997 |
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