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Browse by Category: Main > Electrical & Energy
Class Information
Number: 327/297
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Clock or pulse waveform generating > Plural outputs > Clock bus
Description: Subject matter wherein the clock is applied to a distribution network which distributes a plural series of precisely timed, repetitive voltage pulses to plural devices.










Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8680913 Configurable clock network for programmable logic device Mar. 25, 2014
8659588 Display substrate and display apparatus having the same Feb. 25, 2014
8653875 Semiconductor device, a method of improving a distortion of an output waveform, and an electronic apparatus Feb. 18, 2014
8638251 Delay compensation for sigma delta modulator Jan. 28, 2014
8594170 Clock masking scheme in a mixed-signal system Nov. 26, 2013
8441314 Configurable clock network for programmable logic device May. 14, 2013
8390358 Integrated jitter compliant clock signal generation Mar. 5, 2013
8339209 Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead Dec. 25, 2012
8253484 Configurable clock network for programmable logic device Aug. 28, 2012
8072260 Configurable clock network for programmable logic device Dec. 6, 2011
8060654 Network and method for setting a time-base of a node in the network Nov. 15, 2011
7996705 Signal bus, multilevel input interface and information processor Aug. 9, 2011
7990200 Pulse width modulation control system Aug. 2, 2011
7859329 Configurable clock network for programmable logic device Dec. 28, 2010
7812659 Clock signal circuitry for multi-channel data signaling Oct. 12, 2010
7768334 Semiconductor integrated circuit Aug. 3, 2010
7646237 Configurable clock network for programmable logic device Jan. 12, 2010
7629827 Semiconductor integrated circuit Dec. 8, 2009
7622979 Dynamic voltage scaling for self-timed or racing paths Nov. 24, 2009
7586355 Low skew clock distribution tree Sep. 8, 2009
7323789 Multiple chip package and IC chips Jan. 29, 2008
7286007 Configurable clock network for programmable logic device Oct. 23, 2007
7284143 System and method for reducing clock skew Oct. 16, 2007
7245240 Integrated circuit serializers with two-phase global master clocks Jul. 17, 2007
7233189 Signal propagation circuitry for use on integrated circuits Jun. 19, 2007
7129765 Differential clock tree in an integrated circuit Oct. 31, 2006
7126405 Method and apparatus for a distributed clock generator Oct. 24, 2006
7093153 Method and apparatus for lowering bus clock frequency in a complex integrated data processing system Aug. 15, 2006
7075365 Configurable clock network for programmable logic device Jul. 11, 2006
6956424 Timing of and minimizing external influences on digital signals Oct. 18, 2005
6946870 Control of simultaneous switch noise from multiple outputs Sep. 20, 2005
6911843 Data transfer device for transferring data between blocks of different clock domains Jun. 28, 2005
6904536 Semiconductor circuit and functional block including synchronizing circuit for determining operation timing Jun. 7, 2005
6897684 Input buffer circuit and semiconductor memory device May. 24, 2005
6757352 Real time clock with a power saving counter for embedded systems Jun. 29, 2004
6667644 Device for controlling clock signal phase to reduce clock skew Dec. 23, 2003
6667647 Low power clock distribution methodology Dec. 23, 2003
6639436 Semiconductor integrated circuit with function to start and stop supply of clock signal Oct. 28, 2003
6630855 Clock distribution phase alignment technique Oct. 7, 2003
6624681 Circuit and method for stopping a clock tree while maintaining PLL lock Sep. 23, 2003
6577165 Uni-sized clock buffers Jun. 10, 2003
6573757 Signal line matching technique for ICS/PCBS Jun. 3, 2003
6538489 Clock distributing circuit in programmable logic device Mar. 25, 2003
6522186 Hierarchical clock grid for on-die salphasic clocking Feb. 18, 2003
6483364 Ladder type clock network for reducing skew of clock signals Nov. 19, 2002
6437650 Phase-locked loop or delay-locked loop circuitry for programmable logic devices Aug. 20, 2002
6407607 In and out of phase signal generating circuit Jun. 18, 2002
6388484 Clock control circuit May. 14, 2002
6271729 Phase-locked loop or delay-locked loop circuitry for programmable logic devices Aug. 7, 2001
6268749 Core clock correction in a 2/n mode clocking scheme Jul. 31, 2001

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