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Class Information
Number: 327/216
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Particular stable state circuit (e.g., tristable, etc.) > Circuit having only two stable states (i.e., bistable) > Having at least two cross-coupling paths > Jk type input
Description: Subject matter wherein the multivibrator has a clock input and two additional inputs (the "J" and "K" inputs) which jointly determine the output state of the multivibrator at the application of a clock pulse using the following guidelines: (a) if both "J" and "K" are "HIGH", the multivibrator will change state; (b) if "J" and "K" are both "LOW", the multivibrator will maintain its current state; (c) if "J" = "HIGH" and "K" = "LOW", the multivibrator will go to the "HIGH" state; and (d) if "J" = "LOW" and "K" = "HIGH", the multivibrator will go to the "LOW" state.










Patents under this class:

Patent Number Title Of Patent Date Issued
8618855 Semiconductor device, and display device and electronic device having the same Dec. 31, 2013
8570562 Image forming apparatus and network connection method thereof relates to an image forming apparatus which supports different network connections according to an operation mode Oct. 29, 2013
8181073 SRAM macro test flop May. 15, 2012
8151152 Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method Apr. 3, 2012
8134395 Leakage power optimized structure Mar. 13, 2012
7656211 Dynamic floating input D flip-flop Feb. 2, 2010
7123069 Latch or phase detector device Oct. 17, 2006
6970018 Clocked cycle latch circuit Nov. 29, 2005
6806739 Time-borrowing N-only clocked cycle latch Oct. 19, 2004
6784712 Variable circuit capable of changing the connected states of its flipflops Aug. 31, 2004
6636073 Semiconductor integrated circuit Oct. 21, 2003
6556043 Asynchronous latch design for field programmable gate arrays Apr. 29, 2003
6542016 Level sensitive latch Apr. 1, 2003
6069513 Toggle flip-flop network with a reduced integration area May. 30, 2000
5912576 Clocked register Jun. 15, 1999
5532634 High-integration J-K flip-flop circuit Jul. 2, 1996
5250858 Double-edge triggered memory device and system Oct. 5, 1993
5045715 Circuit for generating stretched clock phases on a cycle by cycle basis Sep. 3, 1991
4958090 Non-current hogging dual phase splitter TTL circuit Sep. 18, 1990
4741006 Up/down counter device with reduced number of discrete circuit elements Apr. 26, 1988
4736395 Logic circuit having a test data loading function Apr. 5, 1988
4607173 Dual-clock edge triggered flip-flop circuits Aug. 19, 1986
4328435 Dynamically switchable logic block for JK/EOR functions May. 4, 1982
4291241 Timing signal generating circuit Sep. 22, 1981
4230957 Logic JK flip-flop structure Oct. 28, 1980
4224534 Tri-state signal conditioning method and circuit Sep. 23, 1980
4002933 Five gate flip-flop Jan. 11, 1977
3997798 Circuit arrangement for gating out pulses and/or pulse gaps whose duration is shorter than a given test period t.sub.p from a sequence of digital pulses present at the input end Dec. 14, 1976











 
 
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