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Class Information
Number: 327/161
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > With delay means
Description: Subject matter including means providing a distinct signal time offset.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622971 |
Delay locked loop circuits and methods of generating clock signals |
Nov. 24, 2009 |
| 7619454 |
Clock generator for semiconductor memory apparatus |
Nov. 17, 2009 |
| 7619456 |
Wide frequency multi-phase signal generator with variable duty ratio and method thereof |
Nov. 17, 2009 |
| 7620133 |
Method and apparatus for a digital-to-phase converter |
Nov. 17, 2009 |
| 7620857 |
Controllable delay device |
Nov. 17, 2009 |
| 7616030 |
Semiconductor device and operation method thereof |
Nov. 10, 2009 |
| 7612622 |
Method and device for determining a duty cycle offset |
Nov. 3, 2009 |
| 7605629 |
Adjusting circuit and method for delay circuit |
Oct. 20, 2009 |
| 7605625 |
Device, system and method of delay calibration |
Oct. 20, 2009 |
| 7605624 |
Delay locked loop (DLL) circuit for generating clock signal for memory device |
Oct. 20, 2009 |
| 7605623 |
Semiconductor memory apparatus with a delay locked loop circuit |
Oct. 20, 2009 |
| 7602257 |
Signal generating circuit |
Oct. 13, 2009 |
| 7602224 |
Semiconductor device having delay locked loop and method for driving the same |
Oct. 13, 2009 |
| 7602223 |
Delay-locked loop circuit and method of generating multiplied clock therefrom |
Oct. 13, 2009 |
| 7599245 |
Output controller capable of generating only necessary control signals based on an activated selection signal |
Oct. 6, 2009 |
| 7583118 |
Delay locked loop circuit |
Sep. 1, 2009 |
| 7583124 |
Delaying stage selecting circuit and method thereof |
Sep. 1, 2009 |
| 7576579 |
DLL circuit and semiconductor device including the same |
Aug. 18, 2009 |
| 7576580 |
Energy efficient clock deskew systems and methods |
Aug. 18, 2009 |
| 7570097 |
Electronic circuit with low noise delay circuit |
Aug. 4, 2009 |
| 7567104 |
Data sampling clock edge placement training for high speed GPU-memory interface |
Jul. 28, 2009 |
| 7560963 |
Delay-locked loop apparatus and delay-locked method |
Jul. 14, 2009 |
| 7557561 |
Electronic device, circuit and test apparatus |
Jul. 7, 2009 |
| 7557627 |
Semiconductor memory device for generating a delay locked clock in early stage |
Jul. 7, 2009 |
| 7557628 |
Method and apparatus for digital phase generation at high frequencies |
Jul. 7, 2009 |
| 7558692 |
Consumption current balance circuit, compensation current amount adjusting method, timing generator, and semiconductor testing apparatus |
Jul. 7, 2009 |
| 7554371 |
Delay locked loop |
Jun. 30, 2009 |
| 7535275 |
High-performance memory interface circuit architecture |
May. 19, 2009 |
| 7535274 |
Delay control circuit |
May. 19, 2009 |
| 7532050 |
Delay locked loop circuit and method |
May. 12, 2009 |
| 7532051 |
Method and apparatus for selection of an internal or external time delay |
May. 12, 2009 |
| 7525364 |
Delay control circuit |
Apr. 28, 2009 |
| 7525363 |
Delay line and delay lock loop |
Apr. 28, 2009 |
| 7525356 |
Low-power, programmable multi-stage delay cell |
Apr. 28, 2009 |
| 7525354 |
Local coarse delay units |
Apr. 28, 2009 |
| 7522686 |
CMOS burst mode clock data recovery circuit using frequency tracking method |
Apr. 21, 2009 |
| 7518423 |
Digital DLL circuit for an interface circuit in a semiconductor memory |
Apr. 14, 2009 |
| 7519087 |
Frequency multiply circuit using SMD, with arbitrary multiplication factor |
Apr. 14, 2009 |
| 7514974 |
Method and apparatus for adjusting on-chip delay with power supply control |
Apr. 7, 2009 |
| 7515003 |
Filter-based lock-in circuits for PLL and fast system startup |
Apr. 7, 2009 |
| 7511544 |
Digital DLL circuit for an interface circuit in a semiconductor memory |
Mar. 31, 2009 |
| 7508245 |
Lock detector and delay-locked loop having the same |
Mar. 24, 2009 |
| 7501869 |
Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication |
Mar. 10, 2009 |
| 7495489 |
Frequency multiplying delay-locked loop |
Feb. 24, 2009 |
| 7493509 |
Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systems |
Feb. 17, 2009 |
| 7492200 |
Delayed locked loop (DLL) |
Feb. 17, 2009 |
| 7489568 |
Delay stage-interweaved analog DLL/PLL |
Feb. 10, 2009 |
| 7489587 |
Semiconductor memory device capable of controlling clock cycle time for reduced power consumption |
Feb. 10, 2009 |
| 7486319 |
Signal generating circuit including delay-locked loop and semiconductor device including signal generating circuit |
Feb. 3, 2009 |
| 7482850 |
Delay locked loop circuit and semiconductor integrated circuit device |
Jan. 27, 2009 |
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