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Class Information
Number: 327/159
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > With feedback > Phase lock loop > With digital element
Description: Subject matter including a device performing Boolean algebra operations.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7471157 |
Low power/zero-offset charge pump circuits for DLLs and PLLs |
Dec. 30, 2008 |
| 7466207 |
Gain calibration of a digital controlled oscillator |
Dec. 16, 2008 |
| 7457392 |
Delay locked loop |
Nov. 25, 2008 |
| 7453958 |
Method and device for extracting a clock frequency underlying a data stream |
Nov. 18, 2008 |
| 7449871 |
System for setting an electrical circuit parameter at a predetermined value |
Nov. 11, 2008 |
| 7449927 |
Delay locked loop circuit |
Nov. 11, 2008 |
| 7449928 |
Semiconductor device |
Nov. 11, 2008 |
| 7447106 |
Delay stage-interweaved analog DLL/PLL |
Nov. 4, 2008 |
| 7439812 |
Auto-ranging phase-locked loop |
Oct. 21, 2008 |
| 7423463 |
Clock capture in clock synchronization circuitry |
Sep. 9, 2008 |
| 7420426 |
Frequency modulated output clock from a digital phase locked loop |
Sep. 2, 2008 |
| 7421048 |
System and method for multimedia delivery in a wireless environment |
Sep. 2, 2008 |
| 7414448 |
Duty cycle correction circuit |
Aug. 19, 2008 |
| 7402821 |
Application of digital frequency and phase synthesis for control of electrode voltage phase in a high-energy ion implantation machine, and a means for accurate calibration of electrode voltage |
Jul. 22, 2008 |
| 7397882 |
Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion |
Jul. 8, 2008 |
| 7391839 |
Accumulator based phase locked loop |
Jun. 24, 2008 |
| 7388415 |
Delay locked loop with a function for implementing locking operation periodically during power down mode and locking operation method of the same |
Jun. 17, 2008 |
| 7386084 |
Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit |
Jun. 10, 2008 |
| 7382678 |
Delay stage-interweaved analog DLL/PLL |
Jun. 3, 2008 |
| 7375557 |
Phase-locked loop and method thereof and a phase-frequency detector and method thereof |
May. 20, 2008 |
| 7375562 |
Phase locked system for generating distributed clocks |
May. 20, 2008 |
| 7372341 |
Noise immunity circuitry for phase locked loops and delay locked loops |
May. 13, 2008 |
| 7368965 |
Clock capture in clock synchronization circuitry |
May. 6, 2008 |
| 7368964 |
Delay locked loop in semiconductor memory device and method for generating divided clock therein |
May. 6, 2008 |
| 7365581 |
Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL |
Apr. 29, 2008 |
| 7358783 |
Voltage, temperature, and process independent programmable phase shift for PLL |
Apr. 15, 2008 |
| 7355464 |
Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency |
Apr. 8, 2008 |
| 7353009 |
Combined transmitter |
Apr. 1, 2008 |
| 7339861 |
PLL clock generator, optical disc drive and method for controlling PLL clock generator |
Mar. 4, 2008 |
| 7339408 |
Generating multi-phase clock signals using hierarchical delays |
Mar. 4, 2008 |
| 7336752 |
Wide frequency range delay locked loop |
Feb. 26, 2008 |
| 7315189 |
Retiming circuits for phase-locked loops |
Jan. 1, 2008 |
| 7312667 |
Statically controlled clock source generator for VCDL clock phase trimming |
Dec. 25, 2007 |
| 7310397 |
Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions |
Dec. 18, 2007 |
| 7298192 |
Digital DLL device, digital DLL control method, and digital DLL control program |
Nov. 20, 2007 |
| 7295053 |
Delay-locked loop circuits |
Nov. 13, 2007 |
| 7285997 |
Delay locked loop circuit and method |
Oct. 23, 2007 |
| 7282973 |
Enhanced DLL phase output scheme |
Oct. 16, 2007 |
| 7271664 |
Phase locked loop circuit |
Sep. 18, 2007 |
| 7268594 |
Direct digital synthesis with low jitter |
Sep. 11, 2007 |
| 7268600 |
Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal |
Sep. 11, 2007 |
| 7268602 |
Method and apparatus for accommodating delay variations among multiple signals |
Sep. 11, 2007 |
| 7269217 |
PWM controller with integrated PLL |
Sep. 11, 2007 |
| 7265636 |
Method of correcting the phase difference between two input signals of a phase-locked loop and associated device |
Sep. 4, 2007 |
| 7265634 |
System and method for phase-locked loop initialization |
Sep. 4, 2007 |
| 7259602 |
Method and apparatus for implementing fault tolerant phase locked loop (PLL) |
Aug. 21, 2007 |
| 7259601 |
Apparatus and method for suppressing jitter within a clock signal generator |
Aug. 21, 2007 |
| 7256657 |
Voltage controlled oscillator having digitally controlled phase adjustment and method therefor |
Aug. 14, 2007 |
| 7253842 |
Locking display pixel clock to input frame rate |
Aug. 7, 2007 |
| 7253669 |
High resolution digital loop circuit |
Aug. 7, 2007 |
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