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Class Information
Number: 327/153
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > Using multiple clocks > With delay means
Description: Subject matter including means providing a distinct signal time offset.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622971 |
Delay locked loop circuits and methods of generating clock signals |
Nov. 24, 2009 |
| 7619454 |
Clock generator for semiconductor memory apparatus |
Nov. 17, 2009 |
| 7620857 |
Controllable delay device |
Nov. 17, 2009 |
| 7605620 |
System and method to improve the efficiency of synchronous mirror delays and delay locked loops |
Oct. 20, 2009 |
| 7599245 |
Output controller capable of generating only necessary control signals based on an activated selection signal |
Oct. 6, 2009 |
| 7583115 |
Delay line off-state control with power reduction |
Sep. 1, 2009 |
| 7525354 |
Local coarse delay units |
Apr. 28, 2009 |
| 7515003 |
Filter-based lock-in circuits for PLL and fast system startup |
Apr. 7, 2009 |
| 7505542 |
Low jitter digital frequency synthesizer with frequency modulation capabilities |
Mar. 17, 2009 |
| 7489587 |
Semiconductor memory device capable of controlling clock cycle time for reduced power consumption |
Feb. 10, 2009 |
| 7487481 |
Receiver circuit for on chip timing adjustment |
Feb. 3, 2009 |
| 7482850 |
Delay locked loop circuit and semiconductor integrated circuit device |
Jan. 27, 2009 |
| 7475301 |
Increment/decrement circuit for performance counter |
Jan. 6, 2009 |
| 7457392 |
Delay locked loop |
Nov. 25, 2008 |
| 7449928 |
Semiconductor device |
Nov. 11, 2008 |
| 7450675 |
Multi-channel receiver, digital edge tuning circuit and method thereof |
Nov. 11, 2008 |
| 7447108 |
Output controller for controlling data output of a synchronous semiconductor memory device |
Nov. 4, 2008 |
| 7447289 |
Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program |
Nov. 4, 2008 |
| 7443742 |
Memory arrangement and method for processing data |
Oct. 28, 2008 |
| 7443743 |
Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
Oct. 28, 2008 |
| 7428286 |
Duty cycle correction apparatus and method for use in a semiconductor memory device |
Sep. 23, 2008 |
| 7423462 |
Clock capture in clock synchronization circuitry |
Sep. 9, 2008 |
| 7423464 |
Phase and amplitude modulator |
Sep. 9, 2008 |
| 7423919 |
Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
Sep. 9, 2008 |
| 7420430 |
Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals |
Sep. 2, 2008 |
| 7421048 |
System and method for multimedia delivery in a wireless environment |
Sep. 2, 2008 |
| 7414444 |
Clock capture in clock synchronization circuitry |
Aug. 19, 2008 |
| 7398412 |
Measure controlled delay with duty cycle control |
Jul. 8, 2008 |
| 7391246 |
Digital high speed programmable delayed locked loop |
Jun. 24, 2008 |
| 7375558 |
Method and apparatus for pre-clocking |
May. 20, 2008 |
| 7336752 |
Wide frequency range delay locked loop |
Feb. 26, 2008 |
| 7327173 |
Delay-locked loop having a pre-shift phase detector |
Feb. 5, 2008 |
| 7319352 |
Phase and amplitude modulator |
Jan. 15, 2008 |
| 7301375 |
Off-chip driver circuit and data output circuit using the same |
Nov. 27, 2007 |
| 7298188 |
Timing adjustment circuit and memory controller |
Nov. 20, 2007 |
| 7279944 |
Clock signal generator with self-calibrating mode |
Oct. 9, 2007 |
| 7259599 |
Semiconductor device |
Aug. 21, 2007 |
| 7239575 |
Delay-locked loop having a pre-shift phase detector |
Jul. 3, 2007 |
| 7237216 |
Clock gating approach to accommodate infrequent additional processing latencies |
Jun. 26, 2007 |
| 7236551 |
Linear half-rate phase detector for clock recovery and method therefor |
Jun. 26, 2007 |
| 7215209 |
Controllable idle time current mirror circuit for switching regulators, phase-locked loops, and delay-locked loops |
May. 8, 2007 |
| 7190198 |
Voltage controlled delay loop with central interpolator |
Mar. 13, 2007 |
| 7190753 |
Method and apparatus for temporally correcting a data signal |
Mar. 13, 2007 |
| 7187599 |
Integrated circuit chip having a first delay circuit trimmed via a second delay circuit |
Mar. 6, 2007 |
| 7180332 |
Clock synchronization circuit |
Feb. 20, 2007 |
| 7168032 |
Data synchronization for a test access port |
Jan. 23, 2007 |
| 7161399 |
System and method to improve the efficiency of synchronous mirror delays and delay locked loops |
Jan. 9, 2007 |
| 7162000 |
Delay locked loop synthesizer with multiple outputs and digital modulation |
Jan. 9, 2007 |
| 7138837 |
Digital phase locked loop circuitry and methods |
Nov. 21, 2006 |
| 7113010 |
Clock distortion detector using a synchronous mirror delay circuit |
Sep. 26, 2006 |
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