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Class Information
Number: 327/152
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > Using multiple clocks > With choice between multiple delayed clocks
Description: Subject matter wherein a single delayed clock is obtained from plural candidates.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622971 |
Delay locked loop circuits and methods of generating clock signals |
Nov. 24, 2009 |
| 7602386 |
Reference clock signal generation circuit, power supply circuit, driver circuit, and electro-optical device |
Oct. 13, 2009 |
| 7599245 |
Output controller capable of generating only necessary control signals based on an activated selection signal |
Oct. 6, 2009 |
| 7587014 |
Digital frequency/phase recovery circuit |
Sep. 8, 2009 |
| 7579889 |
Delay lock loop and phase angle generator |
Aug. 25, 2009 |
| 7543090 |
Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout |
Jun. 2, 2009 |
| 7525354 |
Local coarse delay units |
Apr. 28, 2009 |
| 7505542 |
Low jitter digital frequency synthesizer with frequency modulation capabilities |
Mar. 17, 2009 |
| 7489587 |
Semiconductor memory device capable of controlling clock cycle time for reduced power consumption |
Feb. 10, 2009 |
| 7482848 |
Internal clock generation circuits with improved locking speed and corresponding methods |
Jan. 27, 2009 |
| 7474130 |
Compensation of voltage-to-current converter |
Jan. 6, 2009 |
| 7453970 |
Clock signal selecting apparatus and method that guarantee continuity of output clock signal |
Nov. 18, 2008 |
| 7449928 |
Semiconductor device |
Nov. 11, 2008 |
| 7446578 |
Spread spectrum clock generator |
Nov. 4, 2008 |
| 7443743 |
Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
Oct. 28, 2008 |
| 7436228 |
Variable-bandwidth loop filter methods and apparatus |
Oct. 14, 2008 |
| 7433441 |
System and method for adaptively deskewing parallel data signals relative to a clock |
Oct. 7, 2008 |
| 7423461 |
Phase synchronous circuit |
Sep. 9, 2008 |
| 7423919 |
Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
Sep. 9, 2008 |
| 7296170 |
Clock controller with clock source fail-safe logic |
Nov. 13, 2007 |
| 7286625 |
High-speed clock and data recovery circuit |
Oct. 23, 2007 |
| 7284143 |
System and method for reducing clock skew |
Oct. 16, 2007 |
| 7279944 |
Clock signal generator with self-calibrating mode |
Oct. 9, 2007 |
| 7259599 |
Semiconductor device |
Aug. 21, 2007 |
| 7253670 |
Phase synchronization circuit and semiconductor integrated circuit |
Aug. 7, 2007 |
| 7212598 |
Data buffer-controlled digital clock regenerator |
May. 1, 2007 |
| 7170963 |
Clock recovery method by phase selection |
Jan. 30, 2007 |
| 7162000 |
Delay locked loop synthesizer with multiple outputs and digital modulation |
Jan. 9, 2007 |
| 7138837 |
Digital phase locked loop circuitry and methods |
Nov. 21, 2006 |
| 7098712 |
Register controlled delay locked loop with reduced delay locking time |
Aug. 29, 2006 |
| 7100066 |
Clock distribution device and method in compact PCI based multi-processing system |
Aug. 29, 2006 |
| 7095235 |
Monitoring device, electrical machine tool, current supply device, and associated method of operation |
Aug. 22, 2006 |
| 7069458 |
Parallel data interface and method for high-speed timing adjustment |
Jun. 27, 2006 |
| 7043655 |
Redundant clock synthesizer |
May. 9, 2006 |
| 7031420 |
System and method for adaptively deskewing parallel data signals relative to a clock |
Apr. 18, 2006 |
| 7020794 |
Interleaved delay line for phase locked and delay locked loops |
Mar. 28, 2006 |
| 6998928 |
Digital pulse width modulation |
Feb. 14, 2006 |
| 6956415 |
Modular DLL architecture for generating multiple timings |
Oct. 18, 2005 |
| 6954506 |
Clock signal recovery circuit used in receiver of universal serial bus and method of recovering clock signal |
Oct. 11, 2005 |
| 6928027 |
Virtual dual-port synchronous RAM architecture |
Aug. 9, 2005 |
| 6876186 |
Measurement of circuit delay |
Apr. 5, 2005 |
| 6870410 |
All digital power supply system and method that provides a substantially constant supply voltage over changes in PVT without a band gap reference voltage |
Mar. 22, 2005 |
| 6856658 |
Digital PLL circuit operable in short burst interval |
Feb. 15, 2005 |
| 6807243 |
Delay clock generating apparatus and delay time measuring apparatus |
Oct. 19, 2004 |
| 6798258 |
Apparatus and method for introducing signal delay |
Sep. 28, 2004 |
| 6784752 |
Post-silicon phase offset control of phase locked loop input receiver |
Aug. 31, 2004 |
| 6711226 |
Linearized digital phase-locked loop |
Mar. 23, 2004 |
| 6700722 |
High-speed zero phase restart of a multiphase clock |
Mar. 2, 2004 |
| 6690216 |
System and method for compensating for supply voltage induced clock delay mismatches |
Feb. 10, 2004 |
| 6614863 |
Bit synchronization method and bit synchronization device |
Sep. 2, 2003 |
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