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Class Information
Number: 327/151
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > Using multiple clocks > With counter
Description: Subject matter which includes a device which can total the number of pulses applied thereto.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7613266 |
Binary controlled phase selector with output duty cycle correction |
Nov. 3, 2009 |
| 7587014 |
Digital frequency/phase recovery circuit |
Sep. 8, 2009 |
| 7535981 |
Clock generation circuit and method thereof |
May. 19, 2009 |
| 7519846 |
Detection of an in-band reset |
Apr. 14, 2009 |
| 7505542 |
Low jitter digital frequency synthesizer with frequency modulation capabilities |
Mar. 17, 2009 |
| 7489172 |
DLL driver control circuit |
Feb. 10, 2009 |
| 7475301 |
Increment/decrement circuit for performance counter |
Jan. 6, 2009 |
| 7449928 |
Semiconductor device |
Nov. 11, 2008 |
| 7446578 |
Spread spectrum clock generator |
Nov. 4, 2008 |
| 7436919 |
Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface |
Oct. 14, 2008 |
| 7398412 |
Measure controlled delay with duty cycle control |
Jul. 8, 2008 |
| 7397882 |
Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion |
Jul. 8, 2008 |
| 7368939 |
Data input/output circuit included in semiconductor memory device |
May. 6, 2008 |
| 7345933 |
Qualified data strobe signal for double data rate memory controller module |
Mar. 18, 2008 |
| 7317775 |
Switched deskew on arbitrary data |
Jan. 8, 2008 |
| 7256627 |
Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate |
Aug. 14, 2007 |
| 7212049 |
Digital-control-type phase-composing circuit system |
May. 1, 2007 |
| 7194056 |
Determining phase relationships using digital phase values |
Mar. 20, 2007 |
| 7167031 |
Synchronizing circuit provided with hysteresis phase comparator |
Jan. 23, 2007 |
| 7157948 |
Method and apparatus for calibrating a delay line |
Jan. 2, 2007 |
| 7095353 |
Frequency to digital conversion |
Aug. 22, 2006 |
| 7095254 |
Method for producing a control signal which indicates a frequency error |
Aug. 22, 2006 |
| 7092478 |
Local timer which is used in wireless LAN |
Aug. 15, 2006 |
| 7076014 |
Precise synchronization of distributed systems |
Jul. 11, 2006 |
| 7065169 |
Detection of added or missing forwarding data clock signals |
Jun. 20, 2006 |
| 7005899 |
Frequency division/multiplication with jitter minimization |
Feb. 28, 2006 |
| 6959064 |
Clock recovery PLL |
Oct. 25, 2005 |
| 6952121 |
Prescaling for dividing fast pulsed signal |
Oct. 4, 2005 |
| 6930519 |
Frequency division/multiplication with jitter minimization |
Aug. 16, 2005 |
| 6925139 |
Microprocessor comprising a self-calibrated time base circuit |
Aug. 2, 2005 |
| 6873215 |
Power down system and method for integrated circuits |
Mar. 29, 2005 |
| 6862332 |
Clock reproduction circuit |
Mar. 1, 2005 |
| 6859109 |
Double-data rate phase-locked-loop with phase aligners to reduce clock skew |
Feb. 22, 2005 |
| 6731144 |
Delay lock loop circuit, variable delay circuit, and recording signal compensating circuit |
May. 4, 2004 |
| 6721377 |
Method and circuit configuration for resynchronizing a clock signal |
Apr. 13, 2004 |
| 6714056 |
Frequency division/multiplication with jitter minimization |
Mar. 30, 2004 |
| 6701445 |
Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states |
Mar. 2, 2004 |
| 6657463 |
System for maintaining the stability of a programmable frequency multiplier |
Dec. 2, 2003 |
| 6639958 |
Circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock |
Oct. 28, 2003 |
| 6597753 |
Delay clock generating apparatus and delay time measuring apparatus |
Jul. 22, 2003 |
| 6594330 |
Phase-locked loop with digitally controlled, frequency-multiplying oscillator |
Jul. 15, 2003 |
| 6591370 |
Multinode computer system with distributed clock synchronization system |
Jul. 8, 2003 |
| 6583655 |
Clock control circuit |
Jun. 24, 2003 |
| 6580775 |
Method of detecting frequency of digital phase locked loop |
Jun. 17, 2003 |
| 6573772 |
Method and apparatus for locking self-timed pulsed clock |
Jun. 3, 2003 |
| 6570418 |
Timing adjusting circuit |
May. 27, 2003 |
| 6570946 |
One-hot decoded phase shift prescaler |
May. 27, 2003 |
| 6501310 |
Sampling clock adjusting method, and an interface circuit for displaying digital image |
Dec. 31, 2002 |
| 6492852 |
Pre-divider architecture for low power in a digital delay locked loop |
Dec. 10, 2002 |
| 6489822 |
Delay locked loop with delay control unit for noise elimination |
Dec. 3, 2002 |
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