| |
 |
|
Class Information
Number: 327/150
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > Using multiple clocks > With feedback > Phase lock loop > With digital element
Description: Subject matter including a device performing Boolean algebra operations.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622971 |
Delay locked loop circuits and methods of generating clock signals |
Nov. 24, 2009 |
| 7577225 |
Digital phase-looked loop |
Aug. 18, 2009 |
| 7567100 |
Input clock detection circuit for powering down a PLL-based system |
Jul. 28, 2009 |
| 7555073 |
Automatic frequency control loop circuit |
Jun. 30, 2009 |
| 7545168 |
Clock tree network in a field programmable gate array |
Jun. 9, 2009 |
| 7538591 |
Fast locking phase locked loop for synchronization with an input signal |
May. 26, 2009 |
| 7519140 |
Automatic frequency correction PLL circuit |
Apr. 14, 2009 |
| 7492850 |
Phase locked loop apparatus with adjustable phase shift |
Feb. 17, 2009 |
| 7482850 |
Delay locked loop circuit and semiconductor integrated circuit device |
Jan. 27, 2009 |
| 7477083 |
DLL circuit feeding back ZQ calibration result, and semiconductor device incorporating the same |
Jan. 13, 2009 |
| 7457392 |
Delay locked loop |
Nov. 25, 2008 |
| 7449928 |
Semiconductor device |
Nov. 11, 2008 |
| 7428286 |
Duty cycle correction apparatus and method for use in a semiconductor memory device |
Sep. 23, 2008 |
| 7397882 |
Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion |
Jul. 8, 2008 |
| 7375553 |
Clock tree network in a field programmable gate array |
May. 20, 2008 |
| 7352253 |
Oscillator circuit with tuneable signal delay means |
Apr. 1, 2008 |
| 7336752 |
Wide frequency range delay locked loop |
Feb. 26, 2008 |
| 7332947 |
Method and apparatus for distorting duty cycle of a clock |
Feb. 19, 2008 |
| 7296173 |
Semiconductor integrated circuit |
Nov. 13, 2007 |
| 7259599 |
Semiconductor device |
Aug. 21, 2007 |
| 7253669 |
High resolution digital loop circuit |
Aug. 7, 2007 |
| 7170323 |
Delay locked loop harmonic detector and associated method |
Jan. 30, 2007 |
| 7162001 |
Charge pump with transient current correction |
Jan. 9, 2007 |
| 7132867 |
High resolution digital loop circuit |
Nov. 7, 2006 |
| 7109765 |
Programmable phase shift circuitry |
Sep. 19, 2006 |
| 7088796 |
Phase detector customized for clock synthesis unit |
Aug. 8, 2006 |
| 7076014 |
Precise synchronization of distributed systems |
Jul. 11, 2006 |
| 7049846 |
Clock tree network in a field programmable gate array |
May. 23, 2006 |
| 7005899 |
Frequency division/multiplication with jitter minimization |
Feb. 28, 2006 |
| 6998886 |
Apparatus and method for PLL with equalizing pulse removal |
Feb. 14, 2006 |
| 6987405 |
Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors |
Jan. 17, 2006 |
| 6947498 |
Method and apparatus for performing joint timing recovery of multiple received signals |
Sep. 20, 2005 |
| 6930519 |
Frequency division/multiplication with jitter minimization |
Aug. 16, 2005 |
| 6914463 |
Frequency output generation through alternating between selected frequencies |
Jul. 5, 2005 |
| 6911663 |
Transmission circuit and semiconductor device |
Jun. 28, 2005 |
| 6859109 |
Double-data rate phase-locked-loop with phase aligners to reduce clock skew |
Feb. 22, 2005 |
| 6836164 |
Programmable phase shift circuitry |
Dec. 28, 2004 |
| 6825690 |
Clock tree network in a field programmable gate array |
Nov. 30, 2004 |
| 6826247 |
Digital phase lock loop |
Nov. 30, 2004 |
| 6753710 |
Method and apparatus for generating a clock signal |
Jun. 22, 2004 |
| 6737896 |
Synchronous circuit |
May. 18, 2004 |
| 6714056 |
Frequency division/multiplication with jitter minimization |
Mar. 30, 2004 |
| 6687881 |
Method for optimizing loop bandwidth in delay locked loops |
Feb. 3, 2004 |
| 6657456 |
Programmable logic with on-chip DLL or PLL to distribute clock |
Dec. 2, 2003 |
| 6642754 |
Clock signal generator employing a DDS circuit |
Nov. 4, 2003 |
| 6639958 |
Circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock |
Oct. 28, 2003 |
| 6636575 |
Cascading PLL units for achieving rapid synchronization between digital communications systems |
Oct. 21, 2003 |
| 6583653 |
Method and apparatus for generating a clock signal |
Jun. 24, 2003 |
| 6556640 |
Digital PLL circuit and signal regeneration method |
Apr. 29, 2003 |
| 6529083 |
Clock control circuit |
Mar. 4, 2003 |
|
|
|
