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Class Information
Number: 327/147
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > Using multiple clocks > With feedback > Phase lock loop
Description: Subject matter wherein a circuit compares the phase of the output signal with a reference signal and converts any difference into a correction voltage that changes the phase of the output so it matches that of the reference or input signal.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622966 |
Switchable phase locked loop and method for the operation of a switchable phase locked loop |
Nov. 24, 2009 |
| 7619451 |
Techniques for compensating delays in clock signals on integrated circuits |
Nov. 17, 2009 |
| 7613266 |
Binary controlled phase selector with output duty cycle correction |
Nov. 3, 2009 |
| 7609799 |
Circuit, system, and method for multiplexing signals with reduced jitter |
Oct. 27, 2009 |
| 7605624 |
Delay locked loop (DLL) circuit for generating clock signal for memory device |
Oct. 20, 2009 |
| 7602254 |
System and method for generating signals with a preselected frequency relationship in two steps |
Oct. 13, 2009 |
| 7595671 |
PLL circuit |
Sep. 29, 2009 |
| 7595670 |
Electronic device and method for on chip skew measurement |
Sep. 29, 2009 |
| 7583773 |
Frequency synthesizing device with automatic calibration |
Sep. 1, 2009 |
| 7583774 |
Clock synchroniser |
Sep. 1, 2009 |
| 7579886 |
Phase locked loop with adaptive phase error compensation |
Aug. 25, 2009 |
| 7580498 |
Closed loop control system and method of dynamically changing the loop bandwidth |
Aug. 25, 2009 |
| 7577225 |
Digital phase-looked loop |
Aug. 18, 2009 |
| 7576576 |
Switchable PLL circuit |
Aug. 18, 2009 |
| 7567100 |
Input clock detection circuit for powering down a PLL-based system |
Jul. 28, 2009 |
| 7564280 |
Phase locked loop with small size and improved performance |
Jul. 21, 2009 |
| 7564281 |
Wide-locking range phase locked loop circuit using adaptive post division technique |
Jul. 21, 2009 |
| 7561652 |
High frequency spread spectrum clock generation |
Jul. 14, 2009 |
| 7557624 |
Fractional digital PLL |
Jul. 7, 2009 |
| 7557623 |
Circuit arrangement, in particular phase-locked loop, as well as corresponding method |
Jul. 7, 2009 |
| 7554479 |
Pseudo-multiple sampling methods, systems and devices for analog-to-digital conversion |
Jun. 30, 2009 |
| 7555073 |
Automatic frequency control loop circuit |
Jun. 30, 2009 |
| 7551010 |
PLL circuit and design method thereof |
Jun. 23, 2009 |
| 7551011 |
Constant phase angle control for frequency agile power switching systems |
Jun. 23, 2009 |
| 7541850 |
PLL with low spurs |
Jun. 2, 2009 |
| 7541848 |
PLL circuit |
Jun. 2, 2009 |
| 7538591 |
Fast locking phase locked loop for synchronization with an input signal |
May. 26, 2009 |
| 7539278 |
Programmable transceivers that are able to operate over wide frequency ranges |
May. 26, 2009 |
| 7539473 |
Overshoot reduction in VCO calibration for serial link phase lock loop (PLL) |
May. 26, 2009 |
| 7535270 |
Semiconductor memory device |
May. 19, 2009 |
| 7532029 |
Techniques for reconfiguring programmable circuit blocks |
May. 12, 2009 |
| 7532038 |
Phase detecting circuit having adjustable gain curve and method thereof |
May. 12, 2009 |
| 7528639 |
DLL circuit and method of controlling the same |
May. 5, 2009 |
| 7529329 |
Circuit for adaptive sampling edge position control and a method therefor |
May. 5, 2009 |
| 7526666 |
Derived clock synchronization for reduced skew and jitter |
Apr. 28, 2009 |
| 7521974 |
Translational phase locked loop using a quantized interpolated edge timed synthesizer |
Apr. 21, 2009 |
| 7519113 |
Noise detection device |
Apr. 14, 2009 |
| 7515656 |
Clock recovery circuit and data receiving circuit |
Apr. 7, 2009 |
| 7511543 |
Automatic static phase error and jitter compensation in PLL circuits |
Mar. 31, 2009 |
| 7508245 |
Lock detector and delay-locked loop having the same |
Mar. 24, 2009 |
| 7501865 |
Methods and systems for a digital frequency locked loop for multi-frequency clocking of a multi-core processor |
Mar. 10, 2009 |
| 7501866 |
Delay locked loop circuit |
Mar. 10, 2009 |
| 7501867 |
Power supply noise rejection in PLL or DLL circuits |
Mar. 10, 2009 |
| 7502602 |
Method and apparatus to compensate loop error of phase locked loop |
Mar. 10, 2009 |
| 7495486 |
Semiconductor memory device |
Feb. 24, 2009 |
| 7492195 |
Agile, low phase noise clock synthesizer and jitter attenuator |
Feb. 17, 2009 |
| 7492850 |
Phase locked loop apparatus with adjustable phase shift |
Feb. 17, 2009 |
| 7489172 |
DLL driver control circuit |
Feb. 10, 2009 |
| 7486118 |
Signal generating apparatus and method thereof |
Feb. 3, 2009 |
| 7486120 |
Delay ratio adjusting circuit, delayed pulse generation circuit, and pulse width modulation pulse signal generation device |
Feb. 3, 2009 |
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