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Class Information
Number: 327/145
Name: Miscellaneous active electrical nonlinear devices, circuits, and systems > Signal converting, shaping, or generating > Synchronizing > Using multiple clocks > Having different frequencies
Description: Subject matter wherein the plural clocks have diverse repetition rates.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622965 |
Dual-edge shaping latch/synchronizer for re-aligning edges |
Nov. 24, 2009 |
| 7622961 |
Method and apparatus for late timing transition detection |
Nov. 24, 2009 |
| 7567099 |
Filterless digital frequency locked loop |
Jul. 28, 2009 |
| 7555084 |
System and method of digital system performance enhancement |
Jun. 30, 2009 |
| 7521973 |
Clock-skew tuning apparatus and method |
Apr. 21, 2009 |
| 7519140 |
Automatic frequency correction PLL circuit |
Apr. 14, 2009 |
| 7519925 |
Integrated circuit with dynamically controlled voltage supply |
Apr. 14, 2009 |
| 7482841 |
Differential bang-bang phase detector (BBPD) with latency reduction |
Jan. 27, 2009 |
| 7475269 |
Method and system for fast frequency switch for a power throttle in an integrated device |
Jan. 6, 2009 |
| 7454301 |
Method and apparatus for predicting system noise |
Nov. 18, 2008 |
| 7451338 |
Clock domain crossing |
Nov. 11, 2008 |
| 7447106 |
Delay stage-interweaved analog DLL/PLL |
Nov. 4, 2008 |
| 7443743 |
Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
Oct. 28, 2008 |
| 7423919 |
Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
Sep. 9, 2008 |
| 7421048 |
System and method for multimedia delivery in a wireless environment |
Sep. 2, 2008 |
| 7355483 |
System and method for mitigating phase pulling in a multiple frequency source system |
Apr. 8, 2008 |
| 7334073 |
Method of and apparatus for interfacing buses operating at different speeds |
Feb. 19, 2008 |
| 7319345 |
Wide-range multi-phase clock generator |
Jan. 15, 2008 |
| 7276942 |
Method for configurably enabling pulse clock generation for multiple signaling modes |
Oct. 2, 2007 |
| 7271545 |
Ballast and igniter for a lamp having larger storage capacitor than charge pump capacitor |
Sep. 18, 2007 |
| 7260753 |
Methods and apparatus for providing test access to asynchronous circuits and systems |
Aug. 21, 2007 |
| 7259599 |
Semiconductor device |
Aug. 21, 2007 |
| 7257728 |
Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs |
Aug. 14, 2007 |
| 7231008 |
Fast locking clock and data recovery unit |
Jun. 12, 2007 |
| 7180332 |
Clock synchronization circuit |
Feb. 20, 2007 |
| 7149145 |
Delay stage-interweaved analog DLL/PLL |
Dec. 12, 2006 |
| 7098709 |
Spread-spectrum clock generator |
Aug. 29, 2006 |
| 7061286 |
Synchronization between low frequency and high frequency digital signals |
Jun. 13, 2006 |
| 7038506 |
Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system |
May. 2, 2006 |
| 6985547 |
System and method of digital system performance enhancement |
Jan. 10, 2006 |
| 6982575 |
Clock ratio data synchronizer |
Jan. 3, 2006 |
| 6946886 |
Clock-synchronized serial communication device and semiconductor integrated circuit device |
Sep. 20, 2005 |
| 6943597 |
Hard phase alignment of clock signals with an oscillator controller |
Sep. 13, 2005 |
| 6931561 |
Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components |
Aug. 16, 2005 |
| 6900665 |
Transfer of digital data across asynchronous clock domains |
May. 31, 2005 |
| 6894946 |
METHODS OF OPERATING MEMORY SYSTEMS IN WHICH AN ACTIVE TERMINATION VALUE FOR A MEMORY DEVICE IS DETERMINED AT A LOW CLOCK FREQUENCY AND COMMANDS ARE APPLIED TO THE MEMORY DEVICE AT A HIGHER CL |
May. 17, 2005 |
| 6888412 |
Phase locked loop circuit for reducing electromagnetic interference and control method thereof |
May. 3, 2005 |
| 6879185 |
Low power clock distribution scheme |
Apr. 12, 2005 |
| 6831959 |
Method and system for switching between multiple clock signals in digital circuit |
Dec. 14, 2004 |
| 6823032 |
Telecommunication device including a clock generation unit |
Nov. 23, 2004 |
| 6807658 |
Systems and methods for performing clock gating checks |
Oct. 19, 2004 |
| 6798238 |
Semiconductor integrated circuit |
Sep. 28, 2004 |
| 6794910 |
Method and circuit for synchronizing signals |
Sep. 21, 2004 |
| 6771099 |
Synchronizer with zero metastability |
Aug. 3, 2004 |
| 6760277 |
Arrangement for generating multiple clocks in field programmable gate arrays of a network test system |
Jul. 6, 2004 |
| 6744277 |
Programmable current reference circuit |
Jun. 1, 2004 |
| 6741522 |
Methods and structure for using a higher frequency clock to shorten a master delay line |
May. 25, 2004 |
| 6636086 |
High performance microwave synthesizer using multiple-modulator fractional-N divider |
Oct. 21, 2003 |
| 6611158 |
Method and system using a common reset and a slower reset clock |
Aug. 26, 2003 |
| 6606361 |
Circuits, systems, and methods for providing a single output clock and output data stream from an interface having multiple clocks and an input data stream |
Aug. 12, 2003 |
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