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Class Information
Number: 326/98
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates > Field-effect transistor > Mosfet
Description: Subject matter includes a field-effect transistor having a metallic gate insulated from the channel by an oxide layer (e.g., SiO2
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622961 |
Method and apparatus for late timing transition detection |
Nov. 24, 2009 |
| 7592840 |
Domino circuit with disable feature |
Sep. 22, 2009 |
| 7573300 |
Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same |
Aug. 11, 2009 |
| 7570080 |
Set dominant latch with soft error resiliency |
Aug. 4, 2009 |
| 7567096 |
Circuit device and method of controlling a voltage swing |
Jul. 28, 2009 |
| 7564266 |
Logic state catching circuits |
Jul. 21, 2009 |
| 7557616 |
Limited switch dynamic logic cell based register |
Jul. 7, 2009 |
| 7545177 |
Method and apparatus for leakage current reduction |
Jun. 9, 2009 |
| 7541841 |
Semiconductor integrated circuit |
Jun. 2, 2009 |
| 7539467 |
Low leakage IC input structures including slaved standby current shut-off and increased gain for tighter hysteresis |
May. 26, 2009 |
| 7532036 |
Semiconductor device having a pseudo power supply wiring |
May. 12, 2009 |
| 7498845 |
Power supply switching at circuit block level to reduce integrated circuit input leakage currents |
Mar. 3, 2009 |
| 7492192 |
Logic processing apparatus, semiconductor device and logic circuit |
Feb. 17, 2009 |
| 7489161 |
Method for extending lifetime reliability of digital logic devices through removal of aging mechanisms |
Feb. 10, 2009 |
| 7486107 |
Method for extending lifetime reliability of digital logic devices through reversal of aging mechanisms |
Feb. 3, 2009 |
| 7479806 |
Semiconductor integrated circuit device |
Jan. 20, 2009 |
| 7479807 |
Leakage dependent online process variation tolerant technique for internal static storage node |
Jan. 20, 2009 |
| 7471114 |
Design structure for a current control mechanism for power networks and dynamic logic keeper circuits |
Dec. 30, 2008 |
| 7463067 |
Switch block for FPGA architectures |
Dec. 9, 2008 |
| 7454589 |
Data buffer circuit, interface circuit and control method therefor |
Nov. 18, 2008 |
| 7443205 |
Relatively low standby power |
Oct. 28, 2008 |
| 7429879 |
Clock receiver circuit device, in particular for semi-conductor components |
Sep. 30, 2008 |
| 7429880 |
Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) |
Sep. 30, 2008 |
| 7411432 |
Integrated circuits and complementary CMOS circuits for frequency dividers |
Aug. 12, 2008 |
| 7411425 |
Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit |
Aug. 12, 2008 |
| 7411423 |
Logic activation circuit |
Aug. 12, 2008 |
| 7405606 |
D flip-flop |
Jul. 29, 2008 |
| 7403042 |
Flip-flop, integrated circuit, and flip-flop resetting method |
Jul. 22, 2008 |
| 7400175 |
Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits |
Jul. 15, 2008 |
| 7391233 |
Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms |
Jun. 24, 2008 |
| 7391232 |
Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms |
Jun. 24, 2008 |
| 7388399 |
Domino logic with variable threshold voltage keeper |
Jun. 17, 2008 |
| 7388400 |
Semiconductor integrated circuits with power reduction mechanism |
Jun. 17, 2008 |
| 7389478 |
System and method for designing a low leakage monotonic CMOS logic circuit |
Jun. 17, 2008 |
| 7382157 |
Interconnect driver circuits for dynamic logic |
Jun. 3, 2008 |
| 7382161 |
Accelerated P-channel dynamic register |
Jun. 3, 2008 |
| 7372305 |
Scannable dynamic logic latch circuit |
May. 13, 2008 |
| 7365575 |
Gated clock logic circuit |
Apr. 29, 2008 |
| 7362140 |
Low swing current mode logic family |
Apr. 22, 2008 |
| 7358768 |
XOR-based conditional keeper and an architecture implementing its application to match lines |
Apr. 15, 2008 |
| 7358775 |
Inverting dynamic register with data-dependent hold time reduction mechanism |
Apr. 15, 2008 |
| 7355454 |
Energy recovery boost logic |
Apr. 8, 2008 |
| 7348806 |
Accelerated N-channel dynamic register |
Mar. 25, 2008 |
| 7345519 |
Flip-flop circuit |
Mar. 18, 2008 |
| 7342421 |
CMOS circuit arrangement |
Mar. 11, 2008 |
| 7342423 |
Circuit and method for calculating a logical combination of two input operands |
Mar. 11, 2008 |
| 7339403 |
Clock error detection circuits, methods, and systems |
Mar. 4, 2008 |
| 7336105 |
Dual gate transistor keeper dynamic logic |
Feb. 26, 2008 |
| 7323910 |
Circuit arrangement and method for producing a dual-rail signal |
Jan. 29, 2008 |
| 7307457 |
Apparatus for implementing dynamic data path with interlocked keeper and restore devices |
Dec. 11, 2007 |
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