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Class Information
Number: 326/97
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates > Field-effect transistor > Two or more clocks (e.g., phase clocking, etc.) > Mosfet
Description: Subject matter includes a field-effect transistor having a metallic gate insulated from the channel by an oxide layer (e.g., SiO2
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7626420 |
Method, apparatus, and system for synchronously resetting logic circuits |
Dec. 1, 2009 |
| 7589565 |
Low-power multi-output local clock buffer |
Sep. 15, 2009 |
| 7521969 |
Switch sequencing circuit systems and methods |
Apr. 21, 2009 |
| 7501850 |
Scannable limited switch dynamic logic (LSDL) circuit |
Mar. 10, 2009 |
| 7482840 |
Semiconductor integrated circuit |
Jan. 27, 2009 |
| 7459940 |
Local clock buffer (LCB) with asymmetric inductive peaking |
Dec. 2, 2008 |
| 7454589 |
Data buffer circuit, interface circuit and control method therefor |
Nov. 18, 2008 |
| 7429879 |
Clock receiver circuit device, in particular for semi-conductor components |
Sep. 30, 2008 |
| 7365575 |
Gated clock logic circuit |
Apr. 29, 2008 |
| 7346861 |
Programmable logic devices with two-phase latch circuitry |
Mar. 18, 2008 |
| 7342568 |
Shift register circuit |
Mar. 11, 2008 |
| 7339403 |
Clock error detection circuits, methods, and systems |
Mar. 4, 2008 |
| 7323910 |
Circuit arrangement and method for producing a dual-rail signal |
Jan. 29, 2008 |
| 7317780 |
Shift register circuit |
Jan. 8, 2008 |
| 7301373 |
Asymmetric precharged flip flop |
Nov. 27, 2007 |
| 7282960 |
Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock |
Oct. 16, 2007 |
| 7268590 |
Method and apparatus for implementing subthreshold leakage reduction in LSDL |
Sep. 11, 2007 |
| 7250789 |
Pseudo-CMOS dynamic logic with delayed clocks |
Jul. 31, 2007 |
| 7245157 |
Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers |
Jul. 17, 2007 |
| 7233639 |
Unfooted domino logic circuit and method |
Jun. 19, 2007 |
| 7224190 |
Midcycle latch for power saving and switching reduction |
May. 29, 2007 |
| 7218160 |
Semiconductor integrated circuit |
May. 15, 2007 |
| 7218151 |
Domino logic with variable threshold voltage keeper |
May. 15, 2007 |
| 7215154 |
Maskable dynamic logic |
May. 8, 2007 |
| 7202704 |
Leakage sensing and keeper circuit for proper operation of a dynamic circuit |
Apr. 10, 2007 |
| 7180332 |
Clock synchronization circuit |
Feb. 20, 2007 |
| 7173456 |
Dynamic logic return-to-zero latching mechanism |
Feb. 6, 2007 |
| 7154303 |
Dynamic circuit |
Dec. 26, 2006 |
| 7132856 |
Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors |
Nov. 7, 2006 |
| 7129754 |
Controlled load limited switch dynamic logic circuitry |
Oct. 31, 2006 |
| 7126379 |
Output device for static random access memory |
Oct. 24, 2006 |
| 7123056 |
Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines |
Oct. 17, 2006 |
| 7095252 |
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates |
Aug. 22, 2006 |
| 7088144 |
Conditional precharge design in staticized dynamic flip-flop with clock enable |
Aug. 8, 2006 |
| 7075336 |
Method for distributing clock signals to flip-flop circuits |
Jul. 11, 2006 |
| 6972599 |
Pseudo CMOS dynamic logic with delayed clocks |
Dec. 6, 2005 |
| 6967502 |
Dynamic circuit |
Nov. 22, 2005 |
| 6965254 |
Dynamic logic register |
Nov. 15, 2005 |
| 6940313 |
Dynamic bus repeater with improved noise tolerance |
Sep. 6, 2005 |
| 6940312 |
Low switching power limited switch dynamic logic |
Sep. 6, 2005 |
| 6911846 |
Method and apparatus for a 1 of N signal |
Jun. 28, 2005 |
| 6906556 |
High-speed domino logic with improved cascode keeper |
Jun. 14, 2005 |
| 6867619 |
Shift registers |
Mar. 15, 2005 |
| 6750677 |
Dynamic semiconductor integrated circuit |
Jun. 15, 2004 |
| 6744285 |
Method and apparatus for synchronously transferring data across multiple clock domains |
Jun. 1, 2004 |
| 6693461 |
Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation |
Feb. 17, 2004 |
| 6686776 |
Digital data coincidence determining circuit |
Feb. 3, 2004 |
| 6677783 |
High-speed, state-preserving, race-reducing, wide-pulsed-clock domino design style |
Jan. 13, 2004 |
| 6590423 |
Digital circuits exhibiting reduced power consumption |
Jul. 8, 2003 |
| 6549040 |
Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates |
Apr. 15, 2003 |
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