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Class Information
Number: 326/96
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates > Field-effect transistor > Two or more clocks (e.g., phase clocking, etc.)
Description: Subject matter wherein the logic circuit is responsive to two or more predetermined time-related signals or periodic signals in addition to the input logic signal.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7429879 |
Clock receiver circuit device, in particular for semi-conductor components |
Sep. 30, 2008 |
| 7363560 |
Circuit for and method of determining the location of a defect in an integrated circuit |
Apr. 22, 2008 |
| 7352212 |
Opposite-phase scheme for peak current reduction |
Apr. 1, 2008 |
| 7346861 |
Programmable logic devices with two-phase latch circuitry |
Mar. 18, 2008 |
| 7339403 |
Clock error detection circuits, methods, and systems |
Mar. 4, 2008 |
| 7323909 |
Automatic extension of clock gating technique to fine-grained power gating |
Jan. 29, 2008 |
| 7301373 |
Asymmetric precharged flip flop |
Nov. 27, 2007 |
| 7298171 |
Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices |
Nov. 20, 2007 |
| 7293190 |
Noisy clock test method and apparatus |
Nov. 6, 2007 |
| 7285985 |
Event-driven logic circuit |
Oct. 23, 2007 |
| 7282960 |
Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock |
Oct. 16, 2007 |
| 7282957 |
Semiconductor integrated circuit |
Oct. 16, 2007 |
| 7280628 |
Data capture for a source synchronous interface |
Oct. 9, 2007 |
| 7265589 |
Independent gate control logic circuitry |
Sep. 4, 2007 |
| 7259594 |
Electronic circuit with a chain of processing elements |
Aug. 21, 2007 |
| 7245157 |
Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers |
Jul. 17, 2007 |
| 7230985 |
Look-ahead decision feedback equalizing receiver |
Jun. 12, 2007 |
| 7218160 |
Semiconductor integrated circuit |
May. 15, 2007 |
| 7212039 |
Dynamic logic register |
May. 1, 2007 |
| 7213184 |
Testing of modules operating with different characteristics of control signals using scan based techniques |
May. 1, 2007 |
| 7202704 |
Leakage sensing and keeper circuit for proper operation of a dynamic circuit |
Apr. 10, 2007 |
| 7193444 |
High speed data bit latch circuit |
Mar. 20, 2007 |
| 7180332 |
Clock synchronization circuit |
Feb. 20, 2007 |
| 7154303 |
Dynamic circuit |
Dec. 26, 2006 |
| 7154305 |
Periodic electrical signal frequency monitoring systems and methods |
Dec. 26, 2006 |
| 7142019 |
System and method for reducing power-on transient current magnitude |
Nov. 28, 2006 |
| 7129754 |
Controlled load limited switch dynamic logic circuitry |
Oct. 31, 2006 |
| 7095252 |
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates |
Aug. 22, 2006 |
| 7088144 |
Conditional precharge design in staticized dynamic flip-flop with clock enable |
Aug. 8, 2006 |
| 7075336 |
Method for distributing clock signals to flip-flop circuits |
Jul. 11, 2006 |
| 7061530 |
Semiconductor integrated circuit |
Jun. 13, 2006 |
| 7042250 |
Synchronization of clock signals in a multi-clock domain |
May. 9, 2006 |
| 7019560 |
High voltage level translator |
Mar. 28, 2006 |
| 7005893 |
High-performance clock-powered logic |
Feb. 28, 2006 |
| 6980033 |
Pseudo CMOS dynamic logic with delayed clocks |
Dec. 27, 2005 |
| 6981167 |
Programmable controller with sub-phase clocking scheme |
Dec. 27, 2005 |
| 6967502 |
Dynamic circuit |
Nov. 22, 2005 |
| 6943586 |
Method and system to temporarily modify an output waveform |
Sep. 13, 2005 |
| 6933757 |
Timing method and apparatus for integrated circuit device |
Aug. 23, 2005 |
| 6911846 |
Method and apparatus for a 1 of N signal |
Jun. 28, 2005 |
| 6906556 |
High-speed domino logic with improved cascode keeper |
Jun. 14, 2005 |
| 6901543 |
Utilizing slow ASIC logic BIST to preserve timing integrity across timing domains |
May. 31, 2005 |
| 6901528 |
Minimum latency propagation of variable pulse width signals across clock domains with variable frequencies |
May. 31, 2005 |
| 6867619 |
Shift registers |
Mar. 15, 2005 |
| 6859070 |
Semiconductor integrated circuit device having flip-flops that can be reset easily |
Feb. 22, 2005 |
| 6850092 |
Low latency FIFO circuits for mixed asynchronous and synchronous systems |
Feb. 1, 2005 |
| 6838911 |
Monotonic dynamic static pseudo-NMOS logic circuits |
Jan. 4, 2005 |
| 6798248 |
Non-overlapping clock generation |
Sep. 28, 2004 |
| 6791360 |
Source synchronous interface using variable digital data delay lines |
Sep. 14, 2004 |
| 6791363 |
Multistage, single-rail logic circuitry and method therefore |
Sep. 14, 2004 |
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