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Class Information
Number: 326/95
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates > Field-effect transistor
Description: Subject matter wherein the logic circuit includes a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7626420 |
Method, apparatus, and system for synchronously resetting logic circuits |
Dec. 1, 2009 |
| 7612577 |
Speedpath repair in an integrated circuit |
Nov. 3, 2009 |
| 7602217 |
Level shifter circuit with pre-charge/pre-discharge |
Oct. 13, 2009 |
| 7598774 |
Reduced power consumption limited-switch dynamic logic (LSDL) circuit |
Oct. 6, 2009 |
| 7595665 |
Clock gated circuit |
Sep. 29, 2009 |
| 7592840 |
Domino circuit with disable feature |
Sep. 22, 2009 |
| 7573300 |
Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same |
Aug. 11, 2009 |
| 7570080 |
Set dominant latch with soft error resiliency |
Aug. 4, 2009 |
| 7564266 |
Logic state catching circuits |
Jul. 21, 2009 |
| 7548102 |
Data latch with minimal setup time and launch delay |
Jun. 16, 2009 |
| 7545175 |
Slew rate controlled digital output buffer without resistors |
Jun. 9, 2009 |
| 7545177 |
Method and apparatus for leakage current reduction |
Jun. 9, 2009 |
| 7541841 |
Semiconductor integrated circuit |
Jun. 2, 2009 |
| 7525341 |
Time-balanced multiplexer switching methods and apparatus |
Apr. 28, 2009 |
| 7498845 |
Power supply switching at circuit block level to reduce integrated circuit input leakage currents |
Mar. 3, 2009 |
| 7492203 |
High speed flip-flops and complex gates using the same |
Feb. 17, 2009 |
| 7492192 |
Logic processing apparatus, semiconductor device and logic circuit |
Feb. 17, 2009 |
| 7489161 |
Method for extending lifetime reliability of digital logic devices through removal of aging mechanisms |
Feb. 10, 2009 |
| 7486107 |
Method for extending lifetime reliability of digital logic devices through reversal of aging mechanisms |
Feb. 3, 2009 |
| 7482840 |
Semiconductor integrated circuit |
Jan. 27, 2009 |
| 7479807 |
Leakage dependent online process variation tolerant technique for internal static storage node |
Jan. 20, 2009 |
| 7474122 |
High-performance static programmable logic array |
Jan. 6, 2009 |
| 7471115 |
Error correcting logic system |
Dec. 30, 2008 |
| 7471114 |
Design structure for a current control mechanism for power networks and dynamic logic keeper circuits |
Dec. 30, 2008 |
| 7459940 |
Local clock buffer (LCB) with asymmetric inductive peaking |
Dec. 2, 2008 |
| 7454589 |
Data buffer circuit, interface circuit and control method therefor |
Nov. 18, 2008 |
| 7443205 |
Relatively low standby power |
Oct. 28, 2008 |
| 7427875 |
Flip-flop circuit |
Sep. 23, 2008 |
| 7428568 |
Symmetric cascaded domino carry generate circuit |
Sep. 23, 2008 |
| 7417467 |
Semiconductor integrated circuit |
Aug. 26, 2008 |
| 7417465 |
N-domino output latch |
Aug. 26, 2008 |
| 7411423 |
Logic activation circuit |
Aug. 12, 2008 |
| 7405606 |
D flip-flop |
Jul. 29, 2008 |
| 7403042 |
Flip-flop, integrated circuit, and flip-flop resetting method |
Jul. 22, 2008 |
| 7391233 |
Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms |
Jun. 24, 2008 |
| 7391232 |
Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms |
Jun. 24, 2008 |
| 7388399 |
Domino logic with variable threshold voltage keeper |
Jun. 17, 2008 |
| 7388470 |
Comparator having small size and improved operating speed |
Jun. 17, 2008 |
| 7389478 |
System and method for designing a low leakage monotonic CMOS logic circuit |
Jun. 17, 2008 |
| 7372305 |
Scannable dynamic logic latch circuit |
May. 13, 2008 |
| 7368953 |
Buffer |
May. 6, 2008 |
| 7365575 |
Gated clock logic circuit |
Apr. 29, 2008 |
| 7358775 |
Inverting dynamic register with data-dependent hold time reduction mechanism |
Apr. 15, 2008 |
| 7355455 |
Low power consumption MIS semiconductor device |
Apr. 8, 2008 |
| 7352212 |
Opposite-phase scheme for peak current reduction |
Apr. 1, 2008 |
| 7346861 |
Programmable logic devices with two-phase latch circuitry |
Mar. 18, 2008 |
| 7345519 |
Flip-flop circuit |
Mar. 18, 2008 |
| 7339403 |
Clock error detection circuits, methods, and systems |
Mar. 4, 2008 |
| 7332932 |
Serial link receiver with wide input voltage range and tolerance to high power voltage supply |
Feb. 19, 2008 |
| 7332937 |
Dynamic logic with adaptive keeper |
Feb. 19, 2008 |
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