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Class Information
Number: 326/94
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates > Metastable state prevention
Description: Subject matter including a circuit to prevent the occurrence of an undecided condition at a logic state transition.

Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
8638122 Apparatus for metastability-hardened storage circuits and associated methods Jan. 28, 2014
8559576 Adaptive synchronization circuit Oct. 15, 2013
8395417 Digital noise filter Mar. 12, 2013
8384437 Method and apparatus for gating a clock signal Feb. 26, 2013
8354870 Switching clock sources Jan. 15, 2013
8332800 Method for identifying redundant signal paths for self-gating signals Dec. 11, 2012
8289050 Switching circuits, latches and methods Oct. 16, 2012
8160859 Medium storing logic simulation program, logic simulation apparatus, and logic simulation method Apr. 17, 2012
8143930 Method and apparatus for amplifying a time difference Mar. 27, 2012
8134387 Self-gating synchronizer Mar. 13, 2012
8063682 Semiconductor circuit for performing signal processing Nov. 22, 2011
8049529 Fault triggerred automatic redundancy scrubber Nov. 1, 2011
7982502 Asynchronous circuit representation of synchronous circuit with asynchronous inputs Jul. 19, 2011
7977976 Self-gating synchronizer Jul. 12, 2011
7952391 Digital noise filter May. 31, 2011
7928768 Apparatus for metastability-hardened storage circuits and associated methods Apr. 19, 2011
7888971 Verification support system and method Feb. 15, 2011
7882473 Sequential equivalence checking for asynchronous verification Feb. 1, 2011
7880506 Resolving metastability Feb. 1, 2011
7825696 Even-number-stage pulse delay device Nov. 2, 2010
7795921 Semiconductor integrated circuit and method of reducing noise Sep. 14, 2010
7746116 Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis Jun. 29, 2010
7671633 Glitch free 2-way clock switch Mar. 2, 2010
7667489 Power-on reset circuit for a voltage regulator having multiple power supply voltages Feb. 23, 2010
7650454 Arbiter module providing low metastability failure probability Jan. 19, 2010
7626420 Method, apparatus, and system for synchronously resetting logic circuits Dec. 1, 2009
7484023 Computer system apparatus for stabilizing asynchronous interfaces Jan. 27, 2009
7454589 Data buffer circuit, interface circuit and control method therefor Nov. 18, 2008
7383370 Arbiter circuit and signal arbitration method Jun. 3, 2008
7359468 Apparatus for synchronizing clock and data between two domains having unknown but coherent phase Apr. 15, 2008
7340541 Method of buffering bidirectional digital I/O lines Mar. 4, 2008
7337345 Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal Feb. 26, 2008
7288969 Zero clock delay metastability filtering circuit Oct. 30, 2007
7230985 Look-ahead decision feedback equalizing receiver Jun. 12, 2007
7225283 Asynchronous arbiter with bounded resolution time and predictable output state May. 29, 2007
7202704 Leakage sensing and keeper circuit for proper operation of a dynamic circuit Apr. 10, 2007
7180332 Clock synchronization circuit Feb. 20, 2007
7132858 Logic circuit Nov. 7, 2006
7106091 Circuit configuration and method for detecting an unwanted attack on an integrated circuit Sep. 12, 2006
7095252 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates Aug. 22, 2006
7091742 Fast ring-out digital storage circuit Aug. 15, 2006
7088144 Conditional precharge design in staticized dynamic flip-flop with clock enable Aug. 8, 2006
7075336 Method for distributing clock signals to flip-flop circuits Jul. 11, 2006
7042250 Synchronization of clock signals in a multi-clock domain May. 9, 2006
6995585 System and method for implementing self-timed decoded data paths in integrated circuits Feb. 7, 2006
6960941 Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits Nov. 1, 2005
6958627 Asynchronous pipeline with latch controllers Oct. 25, 2005
6949955 Synchronizing signals between clock domains Sep. 27, 2005
6930522 Method and apparatus to delay signal latching Aug. 16, 2005
6927604 Clock signal selector circuit with reduced probability of erroneous output due to metastability Aug. 9, 2005

1 2 3 4

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