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Class Information
Number: 326/93
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates
Description: Subject matter wherein individual logic stages or gates are responsive to predetermined time-related signals or periodic signals in addition to an input logic signal.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7423449 |
Electronic circuit |
Sep. 9, 2008 |
| 7423455 |
Systems and methods for A 5:1 multiplexer with a one-fifth ratio duty cycle clock |
Sep. 9, 2008 |
| 7420391 |
Circuit arrangement and method for operating a circuit arrangement |
Sep. 2, 2008 |
| 7420403 |
Latch circuit and flip-flop |
Sep. 2, 2008 |
| 7421607 |
Method and apparatus for providing symmetrical output data for a double data rate DRAM |
Sep. 2, 2008 |
| 7417458 |
Gate driving circuit and display apparatus having the same |
Aug. 26, 2008 |
| 7414436 |
Limited switch dynamic logic cell based register |
Aug. 19, 2008 |
| 7414430 |
Programmable logic device having an embedded differential clock tree |
Aug. 19, 2008 |
| 7411413 |
Pulse latch circuit and semiconductor integrated circuit |
Aug. 12, 2008 |
| 7411425 |
Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit |
Aug. 12, 2008 |
| 7400175 |
Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits |
Jul. 15, 2008 |
| 7400178 |
Data output clock selection circuit for quad-data rate interface |
Jul. 15, 2008 |
| 7391403 |
Latch, latch driving method , and flat display apparatus |
Jun. 24, 2008 |
| 7388531 |
Current steering DAC using thin oxide devices |
Jun. 17, 2008 |
| 7382803 |
Hybrid high-speed/low-speed output latch in 10 GBPS interface with half rate clock |
Jun. 3, 2008 |
| 7382161 |
Accelerated P-channel dynamic register |
Jun. 3, 2008 |
| 7382151 |
Method for reducing cross-talk induced source synchronous bus clock jitter |
Jun. 3, 2008 |
| 7372290 |
System and method for using dummy cycles to mask operations in a secure microcontroller |
May. 13, 2008 |
| 7372299 |
Differential clock tree in an integrated circuit |
May. 13, 2008 |
| 7372304 |
System and method for glitch detection in a secure microcontroller |
May. 13, 2008 |
| 7372305 |
Scannable dynamic logic latch circuit |
May. 13, 2008 |
| 7373540 |
System-on-chip having adjustable voltage level and method for the same |
May. 13, 2008 |
| 7368953 |
Buffer |
May. 6, 2008 |
| 7365574 |
General purpose delay logic |
Apr. 29, 2008 |
| 7362125 |
Digital routing switch matrix for digitized radio-frequency signals |
Apr. 22, 2008 |
| 7362135 |
Apparatus and method for clock skew adjustment in a programmable logic fabric |
Apr. 22, 2008 |
| 7358769 |
XOR circuit |
Apr. 15, 2008 |
| 7359468 |
Apparatus for synchronizing clock and data between two domains having unknown but coherent phase |
Apr. 15, 2008 |
| 7355454 |
Energy recovery boost logic |
Apr. 8, 2008 |
| 7352212 |
Opposite-phase scheme for peak current reduction |
Apr. 1, 2008 |
| 7348806 |
Accelerated N-channel dynamic register |
Mar. 25, 2008 |
| 7348797 |
Functional cells for automated I/O timing characterization of an integrated circuit |
Mar. 25, 2008 |
| 7342423 |
Circuit and method for calculating a logical combination of two input operands |
Mar. 11, 2008 |
| 7340541 |
Method of buffering bidirectional digital I/O lines |
Mar. 4, 2008 |
| 7340631 |
Drift-tolerant sync pulse circuit in a sync pulse generator |
Mar. 4, 2008 |
| 7337345 |
Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal |
Feb. 26, 2008 |
| 7336115 |
Redundancy in signal distribution trees |
Feb. 26, 2008 |
| 7332936 |
Semiconductor circuit, display device, electronic apparatus |
Feb. 19, 2008 |
| 7332938 |
Domino logic testing systems and methods |
Feb. 19, 2008 |
| 7332949 |
High speed pulse based flip-flop with a scan function and a data retention function |
Feb. 19, 2008 |
| 7327161 |
Shift register |
Feb. 5, 2008 |
| 7327169 |
Clocked inverter, NAND, NOR and shift register |
Feb. 5, 2008 |
| 7323909 |
Automatic extension of clock gating technique to fine-grained power gating |
Jan. 29, 2008 |
| 7323910 |
Circuit arrangement and method for producing a dual-rail signal |
Jan. 29, 2008 |
| 7320081 |
Clock-signal generation device, communication device, and semiconductor device |
Jan. 15, 2008 |
| 7317339 |
N-domino register with accelerated non-discharge path |
Jan. 8, 2008 |
| 7317780 |
Shift register circuit |
Jan. 8, 2008 |
| 7310007 |
Logic circuit, system for reducing a clock skew, and method for reducing a clock skew |
Dec. 18, 2007 |
| 7304507 |
Modular buffering circuitry for multi-channel transceiver clock and other signals |
Dec. 4, 2007 |
| 7301362 |
Duplicated double checking production rule set for fault-tolerant electronics |
Nov. 27, 2007 |
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