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Class Information
Number: 326/93
Name: Electronic digital logic circuitry > Clocking or synchronizing of logic stages or gates
Description: Subject matter wherein individual logic stages or gates are responsive to predetermined time-related signals or periodic signals in addition to an input logic signal.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7626420 |
Method, apparatus, and system for synchronously resetting logic circuits |
Dec. 1, 2009 |
| 7626425 |
High performance clock-powered logic |
Dec. 1, 2009 |
| 7627773 |
Logic circuit and semiconductor integrated circuit |
Dec. 1, 2009 |
| 7620926 |
Methods and structures for flexible power management in integrated circuits |
Nov. 17, 2009 |
| 7617409 |
System for checking clock-signal correspondence |
Nov. 10, 2009 |
| 7605612 |
Techniques for reducing power requirements of an integrated circuit |
Oct. 20, 2009 |
| 7602211 |
Semiconductor integrated circuit device |
Oct. 13, 2009 |
| 7602217 |
Level shifter circuit with pre-charge/pre-discharge |
Oct. 13, 2009 |
| 7599457 |
Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits |
Oct. 6, 2009 |
| 7592840 |
Domino circuit with disable feature |
Sep. 22, 2009 |
| 7589565 |
Low-power multi-output local clock buffer |
Sep. 15, 2009 |
| 7586334 |
Circuit arrangement and method for processing a dual-rail signal |
Sep. 8, 2009 |
| 7583103 |
Configurable time borrowing flip-flops |
Sep. 1, 2009 |
| 7583106 |
Clock circuitry |
Sep. 1, 2009 |
| 7576568 |
Self-selecting precharged domino logic circuit |
Aug. 18, 2009 |
| 7571341 |
Method and system for fast frequency switch for a power throttle in an integrated device |
Aug. 4, 2009 |
| 7560956 |
Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals |
Jul. 14, 2009 |
| 7557616 |
Limited switch dynamic logic cell based register |
Jul. 7, 2009 |
| 7557606 |
Synchronization of data signals and clock signals for programmable logic devices |
Jul. 7, 2009 |
| 7557610 |
Columnar floorplan |
Jul. 7, 2009 |
| 7550997 |
4-level logic decoder |
Jun. 23, 2009 |
| 7551001 |
Reconfigurable semiconductor integrated circuit and processing assignment method for the same |
Jun. 23, 2009 |
| 7551002 |
Method and apparatus for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature |
Jun. 23, 2009 |
| 7545178 |
Signal encoder and signal decoder |
Jun. 9, 2009 |
| 7535259 |
Clocked inverter, NAND, NOR and shift register |
May. 19, 2009 |
| 7528630 |
High speed flip-flop |
May. 5, 2009 |
| 7526017 |
Transmitting device, receiving device, transmission system, and transmission method |
Apr. 28, 2009 |
| 7518401 |
Differential clock tree in an integrated circuit |
Apr. 14, 2009 |
| 7518408 |
Synchronizing modules in an integrated circuit |
Apr. 14, 2009 |
| 7511535 |
Fine-grained power management of synchronous and asynchronous datapath circuits |
Mar. 31, 2009 |
| 7508237 |
Mainboard, electronic component, and controlling method of logic operation |
Mar. 24, 2009 |
| 7504857 |
Functional cells for automated I/O timing characterization of an integrated circuit |
Mar. 17, 2009 |
| 7498845 |
Power supply switching at circuit block level to reduce integrated circuit input leakage currents |
Mar. 3, 2009 |
| 7499831 |
Timing closure monitoring circuit and method |
Mar. 3, 2009 |
| 7495476 |
Logic circuit, system for reducing a clock skew, and method for reducing a clock skew |
Feb. 24, 2009 |
| 7492192 |
Logic processing apparatus, semiconductor device and logic circuit |
Feb. 17, 2009 |
| 7493461 |
Dynamic phase alignment for resynchronization of captured data |
Feb. 17, 2009 |
| 7483013 |
Semiconductor circuit, display device, and electronic appliance therewith |
Jan. 27, 2009 |
| 7482837 |
System and method for combining signals on a differential I/O link |
Jan. 27, 2009 |
| 7479915 |
Comparator architecture |
Jan. 20, 2009 |
| 7477068 |
System for reducing cross-talk induced source synchronous bus clock jitter |
Jan. 13, 2009 |
| 7478256 |
Coordinating data synchronous triggers on multiple devices |
Jan. 13, 2009 |
| 7475269 |
Method and system for fast frequency switch for a power throttle in an integrated device |
Jan. 6, 2009 |
| 7466723 |
Various methods and apparatuses for lane to lane deskewing |
Dec. 16, 2008 |
| 7456651 |
On-die termination apparatus for semiconductor memory having exact comparison voltage characteristic and method of controlling the same |
Nov. 25, 2008 |
| 7453288 |
Clock translator and parallel to serial converter |
Nov. 18, 2008 |
| 7454589 |
Data buffer circuit, interface circuit and control method therefor |
Nov. 18, 2008 |
| 7443222 |
Dynamic clock control |
Oct. 28, 2008 |
| 7443205 |
Relatively low standby power |
Oct. 28, 2008 |
| 7439773 |
Integrated circuit communication techniques |
Oct. 21, 2008 |
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