Resources Contact Us Home
Browse by Category: Main > Information Technology
Class Information
Number: 326/73
Name: Electronic digital logic circuitry > Interface (e.g., current drive, level shift, etc.) > Logic level shifting (i.e., interface between devices of different logic families) > Field-effect transistor (e.g., jfet, mosfet, etc.) > Ecl to/from mos
Description: Subject matter comprising the interfacing between an emitter-coupled logic device and a complementary MOS device.

Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
7982500 Low-noise PECL output driver Jul. 19, 2011
7969189 Method and system for improved phase noise in a BiCMOS clock driver Jun. 28, 2011
7928765 Tuning high-side and low-side CMOS data-paths in CML-to-CMOS signal converter Apr. 19, 2011
7714614 Serial data receiving apparatus and electronic apparatus using same May. 11, 2010
7688110 System for providing a complementary metal-oxide semiconductor (CMOS) emitter coupled logic (ECL) equivalent input/output (I/O) circuit Mar. 30, 2010
7646219 Translator circuit having internal positive feedback Jan. 12, 2010
7595660 Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus Sep. 29, 2009
7327164 Interface circuit Feb. 5, 2008
7248075 Level shifter with low leakage current Jul. 24, 2007
6956400 Converter from ECL to CMOS and network element for transmitting signals Oct. 18, 2005
6714043 Output buffer having programmable drive current and output voltage limits Mar. 30, 2004
6703864 Buffer circuit Mar. 9, 2004
6696858 Level-shifting circuit Feb. 24, 2004
6593774 CMOS-interfaceable ECL integrated circuit with tri-state and adjustable amplitude outputs Jul. 15, 2003
6563342 CMOS ECL output buffer May. 13, 2003
6556041 Reducing PECL voltage variation Apr. 29, 2003
6535017 CMOS ECL input buffer Mar. 18, 2003
6489811 Logic gate with symmetrical propagation delay from any input to any output and a controlled output pulse width Dec. 3, 2002
6359518 Signal level adjusting circuit using coupling stage for preventing variation from resulting in each operating point of first amplifying stage and second amplifying stage Mar. 19, 2002
6353335 Negative feedback, self-biasing PECL receivers Mar. 5, 2002
6333642 Level converting method and circuit having an intermediate voltage level range and a clamping circuit Dec. 25, 2001
6323683 Low distortion logic level translator Nov. 27, 2001
6320413 Level conversion circuit Nov. 20, 2001
6294932 Input circuit, output circuit, input-output circuit and method of processing input signals Sep. 25, 2001
6121793 Logic device Sep. 19, 2000
6054874 Output driver circuit with switched current source Apr. 25, 2000
6008667 Emitter-coupled logic to CMOS logic converter and method of operation Dec. 28, 1999
5999017 CMOS implemented output buffer circuit for providing ECL level signals Dec. 7, 1999
5933024 ECL to CMOS level translator using delayed feedback for high speed BICMOS applications Aug. 3, 1999
5905386 CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments May. 18, 1999
5900746 Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs May. 4, 1999
5880600 Device for interfacing logic signals from the LLL level to the TTL and CMOS level Mar. 9, 1999
5880601 Signal receiving circuit and digital signal processing system Mar. 9, 1999
5789941 ECL level/CMOS level logic signal interfacing device Aug. 4, 1998
5751167 CMOS output buffer circuit which converts CMOS logic signals to ECL logic signals and which discharges parasitic load capacitances May. 12, 1998
5729156 ECL to CMOS level translator using delayed feedback for high speed BiCMOS applications Mar. 17, 1998
5633602 Low voltage CMOS to low voltage PECL converter May. 27, 1997
5614843 CMOS-PECL level conversion circuit Mar. 25, 1997
5612635 High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage Mar. 18, 1997
5606268 Differential to single-ended CMOS converter Feb. 25, 1997
5600267 Apparatus for a programmable CML to CMOS translator for power/speed adjustment Feb. 4, 1997
5585743 ECL-CMOS level conversion circuit Dec. 17, 1996
5548230 High-speed CMOS pseudo-ECL output driver Aug. 20, 1996
5539333 CMOS receiver circuit Jul. 23, 1996
5525914 CMOS driver circuit Jun. 11, 1996
5495184 High-speed low-power CMOS PECL I/O transmitter Feb. 27, 1996
5469097 Translator circuit with symmetrical switching delays Nov. 21, 1995
5467313 Level shifter and data output buffer having same Nov. 14, 1995
5467048 Semiconductor device with two series-connected complementary misfets of same conduction type Nov. 14, 1995
5455524 CMOS integrated circuit device and data processing system using the same Oct. 3, 1995

1 2 3

  Recently Added Patents
Selective facsimile denial
Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor
Electrode tab for secondary battery and secondary battery using the same
Server-side connection resource pooling
Efficiently emulating computer architecture condition code settings without executing branch instructions
Weak acid recovery system for ethanol separation processes
Synergistic fungicidal interactions of 5-fluorocytosine and other fungicides
  Randomly Featured Patents
Method and apparatus for automated learning and performance evaluation
Process for gibberellic acid production with "Fusarium moniliforme" strains
Programmable weld and machine controller
Catheter connector system
NMR imaging method
Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation
Grooved traverse drum for use in drum winder
Process for biologically preventing dicotyledonous plant diseases using symbiotical bacteria
Drink dispensing device with holding and drip-collecting system for receptacles of different sizes
Intermediates for the synthesis of phthalimidines