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Class Information
Number: 326/50
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.) > Field-effect transistor > Complementary fet`s
Description: Subject matter wherein the logic function unit includes at least two field-effect transistor elements connected in series with their gate terminals tied together, each having a channel of conductivity type opposite that of the other (e.g., p-channel vs. n-channel, etc.).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7514952 |
I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices |
Apr. 7, 2009 |
| 7489158 |
Feedback circuit for line load compensation and reflection reduction |
Feb. 10, 2009 |
| 6946875 |
Universal logic module and ASIC using the same |
Sep. 20, 2005 |
| 6621298 |
Variable grain architecture for FPGA integrated circuits |
Sep. 16, 2003 |
| 6559719 |
Amplifier |
May. 6, 2003 |
| 6552566 |
Logic array circuits using silicon-on-insulator logic |
Apr. 22, 2003 |
| 6531892 |
Bias voltage generator usable with circuit for producing low-voltage differential signals |
Mar. 11, 2003 |
| 6529035 |
Arrangement for improving the ESD protection in a CMOS buffer |
Mar. 4, 2003 |
| 6489806 |
Zero-power logic cell for use in programmable logic devices |
Dec. 3, 2002 |
| 6480054 |
Digital electronic circuit for use in implementing digital logic functions |
Nov. 12, 2002 |
| 6469355 |
Configuration for voltage buffering in a dynamic memory using CMOS technology |
Oct. 22, 2002 |
| 6393603 |
Circuit design method calculating antenna size of conductive member connected to gate oxide film of transistor with approximate expression |
May. 21, 2002 |
| RE37577 |
High speed configuration independent programmable macrocell |
Mar. 12, 2002 |
| 6346827 |
Programmable logic device input/output circuit configurable as reference voltage input circuit |
Feb. 12, 2002 |
| 6288593 |
Digital electronic circuit for use in implementing digital logic functions |
Sep. 11, 2001 |
| 6169419 |
Method and apparatus for reducing standby leakage current using a transistor stack effect |
Jan. 2, 2001 |
| 6107819 |
Universal non volatile logic gate |
Aug. 22, 2000 |
| 6064226 |
Multiple input/output level interface input receiver |
May. 16, 2000 |
| 6034552 |
Output ESD protection using dynamic-floating-gate arrangement |
Mar. 7, 2000 |
| 6028450 |
Programmable input/output circuit with pull-up bias control |
Feb. 22, 2000 |
| 6008670 |
Differential CMOS logic family |
Dec. 28, 1999 |
| 5999018 |
Programmable buffer circuit comprising reduced number of transistors |
Dec. 7, 1999 |
| 5986480 |
Multiple input zero power AND/NOR gate for use in a field programmable gate array (FPGA) |
Nov. 16, 1999 |
| 5923184 |
Ferroelectric transistor logic functions for programming |
Jul. 13, 1999 |
| 5923185 |
Logic circuit programmable to implement at least two logic functions |
Jul. 13, 1999 |
| 5903043 |
Semiconductor device and an arithmetic and logic unit, a signal converter and a signal processing system using the same |
May. 11, 1999 |
| 5898320 |
Programmable interconnect point having reduced crowbar current |
Apr. 27, 1999 |
| 5898316 |
Mode setting circuit of semiconductor device |
Apr. 27, 1999 |
| 5889414 |
Programmable circuits |
Mar. 30, 1999 |
| 5890100 |
Chip temperature monitor using delay lines |
Mar. 30, 1999 |
| 5883528 |
Five volt tolerant TTL/CMOS and CMOS/CMOS voltage conversion circuit |
Mar. 16, 1999 |
| 5877632 |
FPGA with a plurality of I/O voltage levels |
Mar. 2, 1999 |
| 5821770 |
Option decoding with on-chip electrical fuses |
Oct. 13, 1998 |
| 5796128 |
Gate array with fully wired multiplexer circuits |
Aug. 18, 1998 |
| 5751161 |
Update scheme for impedance controlled I/O buffers |
May. 12, 1998 |
| 5742184 |
Microprocessor having a compensated input buffer circuit |
Apr. 21, 1998 |
| 5742178 |
Programmable voltage stabilizing circuit for a programmable integrated circuit device |
Apr. 21, 1998 |
| 5703496 |
Method and apparatus for limiting the slew rate of output drivers by selectively programming the threshold voltage of flash cells connected thereto |
Dec. 30, 1997 |
| 5666071 |
Device and method for programming high impedance states upon select input/output pads |
Sep. 9, 1997 |
| 5663664 |
Programmable drive strength output buffer with slew rate control |
Sep. 2, 1997 |
| 5646546 |
Programmable logic cell having configurable gates and multiplexers |
Jul. 8, 1997 |
| 5621338 |
High speed configuration independent programmable macrocell |
Apr. 15, 1997 |
| 5614844 |
High speed programmable logic architecture |
Mar. 25, 1997 |
| 5612637 |
Supply and interface configurable input/output buffer |
Mar. 18, 1997 |
| 5600267 |
Apparatus for a programmable CML to CMOS translator for power/speed adjustment |
Feb. 4, 1997 |
| 5592107 |
Configurable NAND/NOR element |
Jan. 7, 1997 |
| 5589783 |
Variable input threshold adjustment |
Dec. 31, 1996 |
| 5583451 |
Polarity control circuit which may be used with a ground bounce limiting buffer |
Dec. 10, 1996 |
| 5583454 |
Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function |
Dec. 10, 1996 |
| 5548225 |
Block specific spare circuit |
Aug. 20, 1996 |
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