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Class Information
Number: 326/48
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.) > Bipolar transistor
Description: Subject matter including a semiconductor device of the type having at least three electrodes (emitter, base, and collector), two potential barriers, and having a controlled current flow of both majority and minority carriers (i.e., holes and electrons).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7373569 |
Pulsed flop with scan circuitry |
May. 13, 2008 |
| 7345378 |
Power supply circuit containing multiple DC--DC converters having programmable output current capabilities |
Mar. 18, 2008 |
| 7292066 |
One-time programmable circuit exploiting BJT h.sub.FE degradation |
Nov. 6, 2007 |
| 6975679 |
Configuration fuses for setting PWM options |
Dec. 13, 2005 |
| 6424172 |
Circuit structure for synthesizing time-continual filters |
Jul. 23, 2002 |
| 6393603 |
Circuit design method calculating antenna size of conductive member connected to gate oxide film of transistor with approximate expression |
May. 21, 2002 |
| 5744981 |
Programmable logic cell with input polarity control |
Apr. 28, 1998 |
| 5614844 |
High speed programmable logic architecture |
Mar. 25, 1997 |
| 5563530 |
Multi-function resonant tunneling logic gate and method of performing binary and multi-valued logic |
Oct. 8, 1996 |
| 5329178 |
Integrated circuit device with user-programmable conditional power-down means |
Jul. 12, 1994 |
| 5229662 |
Logic circuit capable of operating with any one of a plurality of alternative voltage supply levels |
Jul. 20, 1993 |
| 5216295 |
Current mode logic circuits employing IGFETS |
Jun. 1, 1993 |
| 5177379 |
Emitter coupled logic circuit with reduced power consumption and high speed |
Jan. 5, 1993 |
| 5155387 |
Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors |
Oct. 13, 1992 |
| 5130573 |
Semiconductor integrated circuit having ECL circuits and a circuit for compensating a capacitive load |
Jul. 14, 1992 |
| 5124588 |
Programmable combinational logic circuit |
Jun. 23, 1992 |
| 5075574 |
Differential cascode current switch (DCCS) logic circuit family with input diodes |
Dec. 24, 1991 |
| 5059819 |
Integrated logic circuit |
Oct. 22, 1991 |
| 5055710 |
Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block |
Oct. 8, 1991 |
| 4950927 |
Logic circuits for forming VLSI logic networks |
Aug. 21, 1990 |
| 4904887 |
Semiconductor integrated circuit apparatus |
Feb. 27, 1990 |
| 4900954 |
Mixed CML/ECL macro circuitry |
Feb. 13, 1990 |
| 4845387 |
Non-stacked ECL type and function |
Jul. 4, 1989 |
| 4829202 |
Semiconductor integrated bipolar switching circuit for controlling passage of signals |
May. 9, 1989 |
| 4782248 |
STL exclusive-or buffer |
Nov. 1, 1988 |
| 4757216 |
Logic circuit for selective performance of logical functions |
Jul. 12, 1988 |
| 4754173 |
Emitter coupled logic latch with boolean logic input gating network |
Jun. 28, 1988 |
| 4748494 |
Lead arrangement for reducing voltage variation |
May. 31, 1988 |
| 4725979 |
Emitter coupled logic circuit having fuse programmable latch/register bypass |
Feb. 16, 1988 |
| 4725744 |
Input buffer circuit and logic circuit using the buffer circuit |
Feb. 16, 1988 |
| 4714841 |
Double-sided logic input differential switch |
Dec. 22, 1987 |
| 4701641 |
Logic network for D/A conversion |
Oct. 20, 1987 |
| 4697102 |
Bipolar logic circuit having two multi-emitter transistors with an emitter of one connected to the collector of the other to prevent saturation |
Sep. 29, 1987 |
| 4638189 |
Fast and gate with programmable output polarity |
Jan. 20, 1987 |
| 4636990 |
Three state select circuit for use in a data processing system or the like |
Jan. 13, 1987 |
| 4628217 |
Fast scan/set testable latch using two levels of series gating with one current source |
Dec. 9, 1986 |
| 4628216 |
Merging of logic function circuits to ECL latch or flip-flop circuit |
Dec. 9, 1986 |
| 4620188 |
Multi-level logic circuit |
Oct. 28, 1986 |
| 4608667 |
Dual mode logic circuit for a memory array |
Aug. 26, 1986 |
| 4604531 |
Imbalance circuits for DC testing |
Aug. 5, 1986 |
| 4531066 |
Variable bias logic circuit |
Jul. 23, 1985 |
| 4528465 |
Semiconductor circuit alternately operative as a data latch and a logic gate |
Jul. 9, 1985 |
| 4458163 |
Programmable architecture logic |
Jul. 3, 1984 |
| 4399377 |
Selectively operable bit-serial logic circuit |
Aug. 16, 1983 |
| 4378508 |
EFL Logic arrays |
Mar. 29, 1983 |
| 4293919 |
Level sensitive scan design (LSSD) system |
Oct. 6, 1981 |
| 4255672 |
Large scale semiconductor integrated circuit device |
Mar. 10, 1981 |
| 4167727 |
Logic circuits incorporating a dual function input |
Sep. 11, 1979 |
| 4160290 |
One-bit multifunction arithmetic and logic circuit |
Jul. 3, 1979 |
| 4157589 |
Arithmetic logic apparatus |
Jun. 5, 1979 |
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