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Class Information
Number: 326/47
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.) > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7449915 |
VPA logic circuits |
Nov. 11, 2008 |
| 7446562 |
Programmable semiconductor device |
Nov. 4, 2008 |
| 7446563 |
Three dimensional integrated circuits |
Nov. 4, 2008 |
| 7439774 |
Multiplexing circuit for decreasing output delay time of output signal |
Oct. 21, 2008 |
| 7432734 |
Versatile logic element and logic array block |
Oct. 7, 2008 |
| 7432735 |
Programmable gate array apparatus and method for switching circuits |
Oct. 7, 2008 |
| 7434192 |
Techniques for optimizing design of a hard intellectual property block for data transmission |
Oct. 7, 2008 |
| 7429870 |
Resilient integrated circuit architecture |
Sep. 30, 2008 |
| 7425843 |
Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM) |
Sep. 16, 2008 |
| 7423453 |
Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
Sep. 9, 2008 |
| 7420389 |
Clock distribution in a configurable IC |
Sep. 2, 2008 |
| 7420392 |
Programmable gate array and embedded circuitry initialization and processing |
Sep. 2, 2008 |
| 7417453 |
System and method for dynamically executing a function in a programmable logic array |
Aug. 26, 2008 |
| 7417454 |
Low-swing interconnections for field programmable gate arrays |
Aug. 26, 2008 |
| 7417456 |
Dedicated logic cells employing sequential logic and control logic functions |
Aug. 26, 2008 |
| 7417457 |
Scalable non-blocking switching network for programmable logic |
Aug. 26, 2008 |
| 7414433 |
Interconnect structure enabling indirect routing in programmable logic |
Aug. 19, 2008 |
| 7414432 |
Dedicated logic cells employing sequential logic and control logic functions |
Aug. 19, 2008 |
| 7414431 |
Dedicated logic cells employing configurable logic and dedicated logic functions |
Aug. 19, 2008 |
| 7408381 |
Circuit for and method of implementing a plurality of circuits on a programmable logic device |
Aug. 5, 2008 |
| 7408382 |
Configurable circuits, IC's, and systems |
Aug. 5, 2008 |
| 7408383 |
FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation |
Aug. 5, 2008 |
| 7400166 |
Digital logic unit reconfigurable in nonvolatile fashion |
Jul. 15, 2008 |
| 7397276 |
Logic block control architectures for programmable logic devices |
Jul. 8, 2008 |
| 7394288 |
Transferring data in a parallel processing environment |
Jul. 1, 2008 |
| 7391236 |
Distributed memory in field-programmable gate array integrated circuit devices |
Jun. 24, 2008 |
| 7388401 |
Input/output circuit device |
Jun. 17, 2008 |
| 7385417 |
Dual slice architectures for programmable logic devices |
Jun. 10, 2008 |
| 7385419 |
Dedicated input/output first in/first out module for a field programmable gate array |
Jun. 10, 2008 |
| 7382157 |
Interconnect driver circuits for dynamic logic |
Jun. 3, 2008 |
| 7378872 |
Programmable logic device architecture with multiple slice types |
May. 27, 2008 |
| 7378871 |
Programmable device with structure for storing configuration information |
May. 27, 2008 |
| 7378874 |
Creating high-drive logic devices from standard gates with minimal use of custom masks |
May. 27, 2008 |
| 7375553 |
Clock tree network in a field programmable gate array |
May. 20, 2008 |
| 7375552 |
Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure |
May. 20, 2008 |
| 7375548 |
SCL type FPGA with multi-threshold transistors and method for forming same |
May. 20, 2008 |
| 7372297 |
Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources |
May. 13, 2008 |
| 7372298 |
Chip with adjustable pinout function and method thereof |
May. 13, 2008 |
| 7368941 |
Dedicated logic cells employing sequential logic and control logic functions |
May. 6, 2008 |
| 7368943 |
Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy |
May. 6, 2008 |
| 7368944 |
Organizations of logic modules in programmable logic devices |
May. 6, 2008 |
| 7365568 |
Method and circuit for reducing programmable logic pin counts for large scale logic |
Apr. 29, 2008 |
| 7362135 |
Apparatus and method for clock skew adjustment in a programmable logic fabric |
Apr. 22, 2008 |
| 7358765 |
Dedicated logic cells employing configurable logic and dedicated logic functions |
Apr. 15, 2008 |
| 7358766 |
Mask-programmable logic device with programmable portions |
Apr. 15, 2008 |
| 7360192 |
Macrocell, integrated circuit device, and electronic instrument |
Apr. 15, 2008 |
| 7360195 |
Block level routing architecture in a field programmable gate array |
Apr. 15, 2008 |
| 7355443 |
Integrated circuit having building blocks |
Apr. 8, 2008 |
| 7352602 |
Configurable inputs and outputs for memory stacking system and method |
Apr. 1, 2008 |
| 7346876 |
ASIC having dense mask-programmable portion and related system development method |
Mar. 18, 2008 |
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