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Class Information
Number: 326/44
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.) > Array (e.g., pla, pal, pld, etc.) > Field effect transistor
Description: Subject matter wherein the logic circuit includes a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7432736 |
Logic basic cell |
Oct. 7, 2008 |
| 7430137 |
Non-volatile memory cells in a field programmable gate array |
Sep. 30, 2008 |
| 7355437 |
Latch-up prevention circuitry for integrated circuits with transistor body biasing |
Apr. 8, 2008 |
| 7193444 |
High speed data bit latch circuit |
Mar. 20, 2007 |
| 7098689 |
Disabling unused/inactive resources in programmable logic devices for static power reduction |
Aug. 29, 2006 |
| 7053654 |
PLD lookup table including transistors of more than one oxide thickness |
May. 30, 2006 |
| 6972986 |
Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown |
Dec. 6, 2005 |
| 6967500 |
Electronic circuit with on-chip programmable terminations |
Nov. 22, 2005 |
| 6894534 |
Dynamic programmable logic array that can be reprogrammed and a method of use |
May. 17, 2005 |
| 6888748 |
Programmable circuit and its method of operation |
May. 3, 2005 |
| 6882177 |
Tristate structures for programmable logic devices |
Apr. 19, 2005 |
| 6857110 |
Design methodology for merging programmable logic into a custom IC |
Feb. 15, 2005 |
| 6774671 |
Multi-purpose transistor array |
Aug. 10, 2004 |
| 6768338 |
PLD lookup table including transistors of more than one oxide thickness |
Jul. 27, 2004 |
| 6724221 |
Circuitry having exclusive-OR and latch function, and method therefor |
Apr. 20, 2004 |
| RE38451 |
Universal logic module with arithmetic capabilities |
Mar. 2, 2004 |
| 6670824 |
Integrated polysilicon fuse and diode |
Dec. 30, 2003 |
| 6650143 |
Field programmable gate array based upon transistor gate oxide breakdown |
Nov. 18, 2003 |
| 6624773 |
Data encryption and signal scrambling using programmable data conversion arrays |
Sep. 23, 2003 |
| 6600341 |
Integrated circuit and associated design method using spare gate islands |
Jul. 29, 2003 |
| 6552566 |
Logic array circuits using silicon-on-insulator logic |
Apr. 22, 2003 |
| 6545504 |
Four state programmable interconnect device for bus line and I/O pad |
Apr. 8, 2003 |
| 6480032 |
Gate array architecture |
Nov. 12, 2002 |
| 6448809 |
FPGA with a plurality of input reference voltage levels |
Sep. 10, 2002 |
| 6433581 |
Configurable dynamic programmable logic array |
Aug. 13, 2002 |
| 6369608 |
Conditioning semiconductor-on-insulator transistors for programmable logic devices |
Apr. 9, 2002 |
| 6366128 |
Circuit for producing low-voltage differential signals |
Apr. 2, 2002 |
| 6359467 |
Dynamic element matching using current-mode butterfly randomization |
Mar. 19, 2002 |
| 6327178 |
Programmable circuit and its method of operation |
Dec. 4, 2001 |
| 6294930 |
FPGA with a plurality of input reference voltage levels |
Sep. 25, 2001 |
| 6275970 |
Evaluation of the design quality of network nodes |
Aug. 14, 2001 |
| 6272655 |
Method of reducing test time for NVM cell-based FPGA |
Aug. 7, 2001 |
| 6236232 |
Multi-purpose transistor array |
May. 22, 2001 |
| 6222383 |
Controlled PMOS load on a CMOS PLA |
Apr. 24, 2001 |
| 6204691 |
FPGA with a plurality of input reference voltage levels grouped into sets |
Mar. 20, 2001 |
| 6188248 |
Output synchronization-free, high-fanin dynamic NOR gate |
Feb. 13, 2001 |
| 6157557 |
CAM cell and memory employing such, used for both field configurable RAM and PLA |
Dec. 5, 2000 |
| 6154049 |
Multiplier fabric for use in field programmable gate arrays |
Nov. 28, 2000 |
| RE36952 |
One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture |
Nov. 14, 2000 |
| 6130555 |
Driver circuitry for programmable logic devices |
Oct. 10, 2000 |
| 6124729 |
Field programmable logic arrays with vertical transistors |
Sep. 26, 2000 |
| 6111428 |
Programmable logic array |
Aug. 29, 2000 |
| 6094369 |
Ferroelectric nonvolatile memory element having capacitors of same dielectric constant and method thereof |
Jul. 25, 2000 |
| 6066959 |
Logic array having multi-level logic planes |
May. 23, 2000 |
| 6057707 |
Programmable logic device incorporating a memory efficient interconnection device |
May. 2, 2000 |
| 6034543 |
Programmable logic array structure having reduced parasitic loading |
Mar. 7, 2000 |
| 6028447 |
FPGA having predictable open-drain drive mode |
Feb. 22, 2000 |
| 6025736 |
Fast reprogrammable logic with active links between cells |
Feb. 15, 2000 |
| 6025735 |
Programmable switch matrix and method of programming |
Feb. 15, 2000 |
| 6005411 |
Monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type |
Dec. 21, 1999 |
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