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Class Information
Number: 326/41
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.) > Array (e.g., pla, pal, pld, etc.) > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6288568 |
FPGA architecture with deep look-up table RAMs |
Sep. 11, 2001 |
| 6288569 |
Memory array with hard and soft decoders |
Sep. 11, 2001 |
| 6288570 |
Logic structure and circuit for fast carry |
Sep. 11, 2001 |
| 6289496 |
Placement of input-output design objects into a programmable gate array supporting multiple voltage standards |
Sep. 11, 2001 |
| 6285211 |
I/O buffer circuit with pin multiplexing |
Sep. 4, 2001 |
| 6285212 |
Block connector splitting in logic block of a field programmable gate array |
Sep. 4, 2001 |
| 6281703 |
Programmable device with an array of programmable cells and interconnection network |
Aug. 28, 2001 |
| 6281704 |
High-performance interconnect |
Aug. 28, 2001 |
| 6278288 |
Programmable logic device with enhanced multiplexing capabilities in interconnect resources |
Aug. 21, 2001 |
| 6278289 |
Content-addressable memory implemented using programmable logic |
Aug. 21, 2001 |
| 6278290 |
Method and circuit for operating programmable logic devices during power-up and stand-by modes |
Aug. 21, 2001 |
| 6278291 |
Programmable logic array devices with interconnect lines of various lengths |
Aug. 21, 2001 |
| 6275970 |
Evaluation of the design quality of network nodes |
Aug. 14, 2001 |
| 6271681 |
PCI-compatible programmable logic devices |
Aug. 7, 2001 |
| 6272655 |
Method of reducing test time for NVM cell-based FPGA |
Aug. 7, 2001 |
| 6269470 |
Efficient routing of conductors between datapaths |
Jul. 31, 2001 |
| 6266746 |
Control apparatus for random access memories |
Jul. 24, 2001 |
| 6263482 |
Programmable logic device having macrocells with selectable product-term inversion |
Jul. 17, 2001 |
| 6262594 |
Apparatus and method for configurable use of groups of pads of a system on chip |
Jul. 17, 2001 |
| 6262595 |
High-speed programmable interconnect |
Jul. 17, 2001 |
| 6262596 |
Configuration bus interface circuit for FPGAS |
Jul. 17, 2001 |
| 6262597 |
FIFO in FPGA having logic elements that include cascadable shift registers |
Jul. 17, 2001 |
| 6262908 |
Field programmable processor devices |
Jul. 17, 2001 |
| 6259271 |
Configuration memory integrated circuit |
Jul. 10, 2001 |
| 6259272 |
Programmable logic array integrated circuit architectures |
Jul. 10, 2001 |
| 6259273 |
Programmable logic device with mixed mode programmable logic array |
Jul. 10, 2001 |
| 6260184 |
Design of an integrated circuit by selectively reducing or maintaining power lines of the device |
Jul. 10, 2001 |
| 6255846 |
Programmable logic devices with enhanced multiplexing capabilities |
Jul. 3, 2001 |
| 6255847 |
Programmable logic device |
Jul. 3, 2001 |
| 6255848 |
Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA |
Jul. 3, 2001 |
| 6255849 |
On-chip self-modification for PLDs |
Jul. 3, 2001 |
| 6256767 |
Demultiplexer for a molecular wire crossbar network (MWCN DEMUX) |
Jul. 3, 2001 |
| 6252419 |
LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device |
Jun. 26, 2001 |
| 6252792 |
Field programmable processor arrays |
Jun. 26, 2001 |
| 6249144 |
Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources |
Jun. 19, 2001 |
| 6249149 |
Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device |
Jun. 19, 2001 |
| 6246254 |
Method and circuit for providing copy protection in an application-specific integrated circuit |
Jun. 12, 2001 |
| 6246259 |
High-speed programmable logic architecture having active CMOS device drivers |
Jun. 12, 2001 |
| 6246260 |
Programmable logic integrated circuit architecture incorporating a global shareable expander |
Jun. 12, 2001 |
| 6242943 |
Programmable multi-standard I/O architecture for FPGAS |
Jun. 5, 2001 |
| 6242945 |
Field programmable gate array with mask programmable I/O drivers |
Jun. 5, 2001 |
| 6242946 |
Embedded memory block with FIFO mode for programmable logic device |
Jun. 5, 2001 |
| 6242947 |
PLD having a window pane architecture with segmented interconnect wiring between logic block arrays |
Jun. 5, 2001 |
| 6243664 |
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
Jun. 5, 2001 |
| 6243779 |
Noise reduction system and method for reducing switching noise in an interface to a large width bus |
Jun. 5, 2001 |
| RE37195 |
Programmable switch for FPGA input/output signals |
May. 29, 2001 |
| 6239611 |
Circuit and method for testing whether a programmable logic device complies with a zero-hold-time requirement |
May. 29, 2001 |
| 6239612 |
Programmable I/O cells with multiple drivers |
May. 29, 2001 |
| 6239615 |
High-performance interconnect |
May. 29, 2001 |
| 6236229 |
Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities |
May. 22, 2001 |
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