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Class Information
Number: 326/41
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.) > Array (e.g., pla, pal, pld, etc.) > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6480027 |
Driver circuitry for programmable logic devices |
Nov. 12, 2002 |
| 6480028 |
Programmable logic device architectures with super-regions having logic regions and memory region |
Nov. 12, 2002 |
| 6476635 |
Programmable number of metal lines and effective metal width along critical paths in a programmable logic device |
Nov. 5, 2002 |
| 6476636 |
Tileable field-programmable gate array architecture |
Nov. 5, 2002 |
| 6472903 |
Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards |
Oct. 29, 2002 |
| 6472904 |
Double data rate input and output in a programmable logic device |
Oct. 29, 2002 |
| 6469540 |
Reconfigurable device having programmable interconnect network suitable for implementing data paths |
Oct. 22, 2002 |
| 6470484 |
System and method for efficient layout of functionally extraneous cells |
Oct. 22, 2002 |
| 6465336 |
Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module |
Oct. 15, 2002 |
| 6466050 |
Method to improve routability in programmable logic devices via prioritized augmented flows |
Oct. 15, 2002 |
| 6466051 |
Multiplexers for efficient PLD logic blocks |
Oct. 15, 2002 |
| 6466052 |
Implementing wide multiplexers in an FPGA using a horizontal chain structure |
Oct. 15, 2002 |
| 6462578 |
Architecture and interconnect scheme for programmable logic circuits |
Oct. 8, 2002 |
| 6462579 |
Partial reconfiguration of a programmable gate array using a bus macro |
Oct. 8, 2002 |
| 6459297 |
System for programming field programmable devices |
Oct. 1, 2002 |
| 6455905 |
Single chip push-pull power transistor device |
Sep. 24, 2002 |
| 6452417 |
I/O cell architecture for CPLDs |
Sep. 17, 2002 |
| 6448808 |
Interconnect structure for a programmable logic device |
Sep. 10, 2002 |
| 6449628 |
Apparatus and method for programmable datapath arithmetic arrays |
Sep. 10, 2002 |
| 6445209 |
FPGA lookup table with NOR gate write decoder and high speed read decoder |
Sep. 3, 2002 |
| 6441641 |
Programmable logic device with partial battery backup |
Aug. 27, 2002 |
| 6441642 |
Multiplexers for efficient PLD logic blocks |
Aug. 27, 2002 |
| 6437389 |
Vertical gate transistors in pass transistor programmable logic arrays |
Aug. 20, 2002 |
| 6437597 |
Methods and circuits for precise edge placement of test signals |
Aug. 20, 2002 |
| 6437598 |
CPLD scalable and array architecture |
Aug. 20, 2002 |
| 6437713 |
Programmable logic device having amplitude and phase modulation communication |
Aug. 20, 2002 |
| 6433578 |
Heterogeneous programmable gate array |
Aug. 13, 2002 |
| 6433579 |
Programmable logic integrated circuit devices with differential signaling capabilities |
Aug. 13, 2002 |
| 6433580 |
Architecture and interconnect scheme for programmable logic circuits |
Aug. 13, 2002 |
| 6433581 |
Configurable dynamic programmable logic array |
Aug. 13, 2002 |
| 6429681 |
Programmable logic device routing architecture to facilitate register re-timing |
Aug. 6, 2002 |
| 6429682 |
Configuration bus interface circuit for FPGAs |
Aug. 6, 2002 |
| 6426648 |
Carry lookahead for programmable logic array |
Jul. 30, 2002 |
| 6426649 |
Architecture for field programmable gate array |
Jul. 30, 2002 |
| 6424171 |
Base cell and two-dimensional array of base cells for programmable logic LSI |
Jul. 23, 2002 |
| 6420902 |
Field programmable logic arrays with transistors with vertical gates |
Jul. 16, 2002 |
| 6417689 |
Method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device |
Jul. 9, 2002 |
| 6417690 |
Floor plan for scalable multiple level tab oriented interconnect architecture |
Jul. 9, 2002 |
| 6417691 |
Communication device with configurable module interface |
Jul. 9, 2002 |
| 6417692 |
Programmable I/O cells with multiple drivers |
Jul. 9, 2002 |
| 6417693 |
Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency |
Jul. 9, 2002 |
| 6417694 |
Programmable logic device with hierarchical interconnection resources |
Jul. 9, 2002 |
| 6414513 |
Customized system-readable hardware/firmware integrated circuit version information |
Jul. 2, 2002 |
| 6414514 |
Logic device architecture and method of operation |
Jul. 2, 2002 |
| 6414518 |
Circuitry for a low internal voltage integrated circuit |
Jul. 2, 2002 |
| 6411124 |
Programmable logic device logic modules with shift register capabilities |
Jun. 25, 2002 |
| 6407576 |
Interconnection and input/output resources for programmable logic integrated circuit devices |
Jun. 18, 2002 |
| 6404224 |
Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time |
Jun. 11, 2002 |
| 6404225 |
Integrated circuit incorporating a programmable cross-bar switch |
Jun. 11, 2002 |
| 6404226 |
Integrated circuit with standard cell logic and spare gates |
Jun. 11, 2002 |
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