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Class Information
Number: 326/37
Name: Electronic digital logic circuitry > Multifunctional or programmable (e.g., universal, etc.)
Description: Subject matter including (a) a logic circuit capable of either producing different logic function operations from the same logic element or providing a particular, selected (i.e., programmed) logic operation from plural logic elements (e.g., an array, etc.) or (b) details related to the actual setting or programming of the desired logic functions in such a logic circuit.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7626420 |
Method, apparatus, and system for synchronously resetting logic circuits |
Dec. 1, 2009 |
| 7622950 |
GPIO mux/dynamic port configuration |
Nov. 24, 2009 |
| 7620758 |
System and method for fast activation and playing using a multimedia playback control module to load and execute core program |
Nov. 17, 2009 |
| 7620924 |
Base platforms with combined ASIC and FPGA features and process of using the same |
Nov. 17, 2009 |
| 7612581 |
Apparatus for dynamic deployment of pin functions on a chip |
Nov. 3, 2009 |
| 7602212 |
Flexible high-speed serial interface architectures for programmable integrated circuit devices |
Oct. 13, 2009 |
| 7598767 |
Multi-standard data communication interface circuitry for programmable logic devices |
Oct. 6, 2009 |
| 7596774 |
Hard macro with configurable side input/output terminals, for a subsystem |
Sep. 29, 2009 |
| 7592832 |
Adjustable transistor body bias circuitry |
Sep. 22, 2009 |
| 7589648 |
Data decompression |
Sep. 15, 2009 |
| 7589557 |
Reversible input/output delay line for bidirectional input/output blocks |
Sep. 15, 2009 |
| 7589651 |
Flexible signal detect for programmable logic device serial interface |
Sep. 15, 2009 |
| 7590904 |
Systems and methods for detecting a failure event in a field programmable gate array |
Sep. 15, 2009 |
| 7586430 |
Integrated circuit comprising a mixed signal single-wire interface and method for operating the same |
Sep. 8, 2009 |
| 7579863 |
Circuit and method for reducing pin count of chip |
Aug. 25, 2009 |
| 7570076 |
Segmented programmable capacitor array for improved density and reduced leakage |
Aug. 4, 2009 |
| 7570077 |
Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements |
Aug. 4, 2009 |
| 7571413 |
Testing circuitry for programmable logic devices with selectable power supply voltages |
Aug. 4, 2009 |
| 7567628 |
Symmetric differential slicer |
Jul. 28, 2009 |
| 7557610 |
Columnar floorplan |
Jul. 7, 2009 |
| 7550994 |
Programmable logic device with on-chip nonvolatile user memory |
Jun. 23, 2009 |
| 7550324 |
Interface port for electrically programmed fuses in a programmable logic device |
Jun. 23, 2009 |
| 7549138 |
Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
Jun. 16, 2009 |
| 7541832 |
Low power, race free programmable logic arrays |
Jun. 2, 2009 |
| 7538577 |
System and method for configuring a field programmable gate array |
May. 26, 2009 |
| 7535255 |
Logic integrated circuit having dynamic substitution function, information processing apparatus using the same, and dynamic substitution method of logic integrated circuit |
May. 19, 2009 |
| 7536615 |
Logic analyzer systems and methods for programmable logic devices |
May. 19, 2009 |
| 7533282 |
Logic circuit apparatus for selectively assigning a plurality of circuit data to a plurality of programmable logic circuits for minimizing total power while maintaining necessary processing pe |
May. 12, 2009 |
| 7532027 |
Deliberate destruction of integrated circuits |
May. 12, 2009 |
| 7525340 |
Programmable logic device architecture for accommodating specialized circuitry |
Apr. 28, 2009 |
| 7518400 |
Barrel shifter implemented on a configurable integrated circuit |
Apr. 14, 2009 |
| 7504858 |
Configurable integrated circuit with parallel non-neighboring offset connections |
Mar. 17, 2009 |
| 7501854 |
True/complement generator having relaxed setup time via self-resetting circuitry |
Mar. 10, 2009 |
| 7502920 |
Hierarchical storage architecture for reconfigurable logic configurations |
Mar. 10, 2009 |
| 7498839 |
Low power zones for programmable logic devices |
Mar. 3, 2009 |
| 7492182 |
Non-volatile look-up table for an FPGA |
Feb. 17, 2009 |
| 7492183 |
Programmable system on a chip for power-supply voltage and current monitoring and control |
Feb. 17, 2009 |
| 7492188 |
Interconnection and input/output resources for programmable logic integrated circuit devices |
Feb. 17, 2009 |
| 7489164 |
Multi-port memory devices |
Feb. 10, 2009 |
| 7489181 |
Circuit which can be programmed using a resistor and which has a reference current source |
Feb. 10, 2009 |
| 7475315 |
Configurable built in self test circuitry for testing memory arrays |
Jan. 6, 2009 |
| 7474119 |
Logic circuit apparatus and timeshare operating method of a programmable logic circuit |
Jan. 6, 2009 |
| 7471103 |
Method for implementing complex logic within a memory array |
Dec. 30, 2008 |
| 7453286 |
Comparator and method of implementing a comparator in a device having programmable logic |
Nov. 18, 2008 |
| 7454556 |
Method to program non-JTAG attached devices or memories using a PLD and its associated JTAG interface |
Nov. 18, 2008 |
| 7451425 |
Determining controlling pins for a tile module of a programmable logic device |
Nov. 11, 2008 |
| 7451426 |
Application specific configurable logic IP |
Nov. 11, 2008 |
| 7444276 |
Hardware acceleration system for logic simulation using shift register as local cache |
Oct. 28, 2008 |
| 7444456 |
SRAM bus architecture and interconnect to an FPGA |
Oct. 28, 2008 |
| 7439774 |
Multiplexing circuit for decreasing output delay time of output signal |
Oct. 21, 2008 |
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