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Class Information
Number: 326/23
Name: Electronic digital logic circuitry > Signal sensitivity or transmission integrity > Input noise margin enhancement > With field effect-transistor
Description: Subject matter including a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7598773 |
Radiation hardened logic circuits |
Oct. 6, 2009 |
| 7595664 |
Repeater circuit having different operating and reset voltage ranges, and methods thereof |
Sep. 29, 2009 |
| 7592839 |
Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability |
Sep. 22, 2009 |
| 7412635 |
Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits |
Aug. 12, 2008 |
| 7375556 |
Advanced repeater utilizing signal distribution delay |
May. 20, 2008 |
| 7362126 |
Floating CMOS input circuit that does not draw DC current |
Apr. 22, 2008 |
| 7321238 |
Over-voltage tolerant multifunction input stage |
Jan. 22, 2008 |
| 7304503 |
Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability |
Dec. 4, 2007 |
| 7295041 |
Circuits and methods for detecting and assisting wire transitions |
Nov. 13, 2007 |
| 7282946 |
Delay-insensitive data transfer circuit using current-mode multiple-valued logic |
Oct. 16, 2007 |
| 7262636 |
Method and system for a circuit for timing sensitive applications |
Aug. 28, 2007 |
| 7256609 |
Data acceleration device and data transmission apparatus using the same |
Aug. 14, 2007 |
| 7215135 |
Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions |
May. 8, 2007 |
| 7196538 |
Data acceleration device and data transmission apparatus using the same |
Mar. 27, 2007 |
| 7180325 |
Data input buffer in semiconductor device |
Feb. 20, 2007 |
| 7173455 |
Repeater circuit having different operating and reset voltage ranges, and methods thereof |
Feb. 6, 2007 |
| 7164292 |
Reducing electrical noise during bus turnaround in signal transfer systems |
Jan. 16, 2007 |
| 7142018 |
Circuits and methods for detecting and assisting wire transitions |
Nov. 28, 2006 |
| 7123045 |
Semiconductor integrated circuit device |
Oct. 17, 2006 |
| 7119580 |
Repeater circuit with high performance repeater mode and normal repeater mode |
Oct. 10, 2006 |
| 7116126 |
Intelligent delay insertion based on transition |
Oct. 3, 2006 |
| 7091741 |
Input buffer capable of reducing input capacitance seen by input signal |
Aug. 15, 2006 |
| 6888370 |
Dynamically adjustable termination impedance control techniques |
May. 3, 2005 |
| 6870389 |
Differential circuit with current overshoot suppression |
Mar. 22, 2005 |
| 6825687 |
Selective cooling of an integrated circuit for minimizing power loss |
Nov. 30, 2004 |
| 6823293 |
Hierarchical power supply noise monitoring device and system for very large scale integrated circuits |
Nov. 23, 2004 |
| 6798236 |
Output buffer circuit with power supply voltages different from a power supply voltage applied to an internal circuit |
Sep. 28, 2004 |
| 6720803 |
Driver circuit |
Apr. 13, 2004 |
| 6710627 |
Dynamic CMOS circuits with individually adjustable noise immunity |
Mar. 23, 2004 |
| 6631487 |
On-line testing of field programmable gate array resources |
Oct. 7, 2003 |
| 6577152 |
Noise suppression circuit for suppressing above-ground noises |
Jun. 10, 2003 |
| 6525559 |
Fail-safe circuit with low input impedance using active-transistor differential-line terminators |
Feb. 25, 2003 |
| 6496031 |
Method for calculating the P/N ratio of a static gate based on input voltages |
Dec. 17, 2002 |
| 6456111 |
Receiver circuit for a complementary signal |
Sep. 24, 2002 |
| 6429690 |
Programmable linear transconductor circuit |
Aug. 6, 2002 |
| 6188244 |
Hysteresis input buffer |
Feb. 13, 2001 |
| 6157203 |
Input circuit with improved operating margin using a single input differential circuit |
Dec. 5, 2000 |
| 6154059 |
High performance output buffer |
Nov. 28, 2000 |
| 6114872 |
Differential input circuit |
Sep. 5, 2000 |
| 6111425 |
Very low power logic circuit family with enhanced noise immunity |
Aug. 29, 2000 |
| 6094062 |
Coupled noise reduction circuitry |
Jul. 25, 2000 |
| 6084457 |
Method and apparatus for clamping a high-speed digital signal delivered over a transmission line |
Jul. 4, 2000 |
| 6054876 |
Buffer circuit |
Apr. 25, 2000 |
| 5982218 |
Input circuit provided in a semiconductor integrated circuit, used in high-speed small-amplitude signal transmission system |
Nov. 9, 1999 |
| 5977795 |
Enhanced low voltage TTL interface |
Nov. 2, 1999 |
| 5939908 |
Dual FET driver circuit |
Aug. 17, 1999 |
| 5929669 |
Output buffer circuit for semiconductor memory devices |
Jul. 27, 1999 |
| 5801549 |
Simultaneous transmission bidirectional repeater and initialization mechanism |
Sep. 1, 1998 |
| 5696456 |
Enhanced low voltage TTL interface |
Dec. 9, 1997 |
| 5668449 |
Motor with input-controlled high side driver |
Sep. 16, 1997 |
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