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Class Information
Number: 326/22
Name: Electronic digital logic circuitry > Signal sensitivity or transmission integrity > Input noise margin enhancement
Description: Subject matter having a circuit to reduce the possibility of switching due to noise input instead of signal input.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7609799 |
Circuit, system, and method for multiplexing signals with reduced jitter |
Oct. 27, 2009 |
| 7583753 |
Methods and transmitters for loop-back adaptive pre-emphasis data transmission |
Sep. 1, 2009 |
| 7474117 |
Bi-directional universal serial bus booster circuit |
Jan. 6, 2009 |
| 7436214 |
Pseudo differential current mode receiver |
Oct. 14, 2008 |
| 7409659 |
System and method for suppressing crosstalk glitch in digital circuits |
Aug. 5, 2008 |
| 7394281 |
Bi-directional universal serial bus booster circuit |
Jul. 1, 2008 |
| 7339396 |
Method and apparatus for ameliorating the effects of noise generated by a bus interface |
Mar. 4, 2008 |
| 7332930 |
Noise canceller circuit |
Feb. 19, 2008 |
| 7323907 |
Pre-emphasis driver control |
Jan. 29, 2008 |
| 7315182 |
Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control |
Jan. 1, 2008 |
| 7233164 |
Offset cancellation in a multi-level signaling system |
Jun. 19, 2007 |
| 7218135 |
Method and apparatus for reducing noise in a dynamic manner |
May. 15, 2007 |
| 7180325 |
Data input buffer in semiconductor device |
Feb. 20, 2007 |
| 7170312 |
Systems and methods for reducing timing variations by adjusting buffer drivability |
Jan. 30, 2007 |
| 7143381 |
Resonance reduction arrangements |
Nov. 28, 2006 |
| 7116126 |
Intelligent delay insertion based on transition |
Oct. 3, 2006 |
| 7091741 |
Input buffer capable of reducing input capacitance seen by input signal |
Aug. 15, 2006 |
| 6925559 |
Reducing effects of transmission line reflections by changing transmission line pedestal voltage or recever threshold voltage while monitoring for irregular synchronization |
Aug. 2, 2005 |
| 6876224 |
Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveforms |
Apr. 5, 2005 |
| 6873178 |
Skewed bus driving method and circuit |
Mar. 29, 2005 |
| 6870389 |
Differential circuit with current overshoot suppression |
Mar. 22, 2005 |
| 6842044 |
Glitch-free receivers for bi-directional, simultaneous data bus |
Jan. 11, 2005 |
| 6794893 |
Pad circuit and method for automatically adjusting gain for the same |
Sep. 21, 2004 |
| 6703869 |
Method and apparatus for low latency distribution of logic signals |
Mar. 9, 2004 |
| 6675331 |
Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch |
Jan. 6, 2004 |
| 6661255 |
Interface circuit |
Dec. 9, 2003 |
| 6563344 |
Buffer circuit for the reception of a clock signal |
May. 13, 2003 |
| 6549033 |
Signal processing device and process and electrical apparatus comprising such a device |
Apr. 15, 2003 |
| 6542003 |
Circuit configuration and method for directly electrically isolated broadband transmission |
Apr. 1, 2003 |
| 6538473 |
High speed digital signal buffer and method |
Mar. 25, 2003 |
| 6515512 |
Capacitively coupled re-referencing circuit with transient correction |
Feb. 4, 2003 |
| 6476640 |
Method for buffering an input signal |
Nov. 5, 2002 |
| 6429690 |
Programmable linear transconductor circuit |
Aug. 6, 2002 |
| 6351158 |
Floating gate circuit for backwards driven MOS output driver |
Feb. 26, 2002 |
| 6184717 |
Digital signal transmitter and receiver using source based reference logic levels |
Feb. 6, 2001 |
| 6137306 |
Input buffer having adjustment function for suppressing skew |
Oct. 24, 2000 |
| 6094062 |
Coupled noise reduction circuitry |
Jul. 25, 2000 |
| 6091265 |
Low voltage CMOS input buffer with undershoot/overshoot protection |
Jul. 18, 2000 |
| 5990700 |
Input buffer circuit and method |
Nov. 23, 1999 |
| 5949248 |
Apparatus and method for dynamic hardening of a digital circuit |
Sep. 7, 1999 |
| 5910736 |
Differential-type data transmitter |
Jun. 8, 1999 |
| 5894229 |
Input circuit of semiconductor memory device for generating an internal signal in accordance with an external signal and for applying it to an internal circuitry |
Apr. 13, 1999 |
| 5612630 |
Asynchronous self-adjusting input circuit |
Mar. 18, 1997 |
| 5565803 |
Digital input threshold switching circuit |
Oct. 15, 1996 |
| 5539337 |
Clock noise filter for integrated circuits |
Jul. 23, 1996 |
| 5517140 |
Sample and hold circuit |
May. 14, 1996 |
| 5349246 |
Input buffer with hysteresis characteristics |
Sep. 20, 1994 |
| 5336948 |
Active negation emulator |
Aug. 9, 1994 |
| 5315176 |
Differential ECL circuit |
May. 24, 1994 |
| 5220211 |
High speed bus transceiver with fault tolerant design for hot pluggable applications |
Jun. 15, 1993 |
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