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Class Information
Number: 326/15
Name: Electronic digital logic circuitry > Reliability > Parasitic prevention in integrated circuit structure
Description: Subject matter wherein the logic device is part of a monolithic integrated circuit, and is intended to prevent an unwanted interaction between circuit components in the monolithic integrated circuit.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7504851 |
Fault tolerant asynchronous circuits |
Mar. 17, 2009 |
| 7501849 |
Latch-up prevention circuitry for integrated circuits with transistor body biasing |
Mar. 10, 2009 |
| 7499676 |
Low voltage differential signaling transceiver |
Mar. 3, 2009 |
| 7427872 |
Asynchronous coupling and decoupling of chips |
Sep. 23, 2008 |
| 7427871 |
Fault tolerant integrated circuit architecture |
Sep. 23, 2008 |
| 7245159 |
Protecting one-hot logic against short-circuits during power-on |
Jul. 17, 2007 |
| 7212027 |
Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal |
May. 1, 2007 |
| 7155360 |
Process variation detector and process variation detecting method |
Dec. 26, 2006 |
| 7064574 |
PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets |
Jun. 20, 2006 |
| 7061735 |
Semiconductor device |
Jun. 13, 2006 |
| 7019550 |
Leakage testing for differential signal transceiver |
Mar. 28, 2006 |
| 6978434 |
Method of designing wiring structure of semiconductor device and wiring structure designed accordingly |
Dec. 20, 2005 |
| 6917221 |
Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits |
Jul. 12, 2005 |
| 6903571 |
Programmable systems and devices with multiplexer circuits providing enhanced capabilities for triple modular redundancy |
Jun. 7, 2005 |
| 6842042 |
Global chip interconnect |
Jan. 11, 2005 |
| 6810511 |
Method of designing active region pattern with shift dummy pattern |
Oct. 26, 2004 |
| 6806738 |
Semiconductor circuit device capable of high speed decoding |
Oct. 19, 2004 |
| 6801051 |
System and method for providing capacitive spare fill cells in an integrated circuit |
Oct. 5, 2004 |
| 6744273 |
Semiconductor device capable of reducing noise to signal line |
Jun. 1, 2004 |
| 6653857 |
Increasing implicit decoupling capacitance using asymmetric shieldings |
Nov. 25, 2003 |
| 6577178 |
Transient gate tunneling current control |
Jun. 10, 2003 |
| 6456117 |
Shield circuit and integrated circuit in which the shield circuit is used |
Sep. 24, 2002 |
| 6288572 |
Method and apparatus for reducing leakage in dynamic silicon-on-insulator logic circuits |
Sep. 11, 2001 |
| 6285208 |
Activation speed of signal wiring line in semiconductor integrated circuit |
Sep. 4, 2001 |
| 6188247 |
Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insu |
Feb. 13, 2001 |
| 6124735 |
Method and apparatus for a N-nary logic circuit using capacitance isolation |
Sep. 26, 2000 |
| 6094068 |
CMOS logic circuit and method of driving the same |
Jul. 25, 2000 |
| 6094072 |
Methods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuits |
Jul. 25, 2000 |
| 5990523 |
Circuit structure which avoids latchup effect |
Nov. 23, 1999 |
| 5973513 |
Integrated circuit arrangement with an open-collector transistor designed as npn transistor |
Oct. 26, 1999 |
| 5519340 |
Line driver having maximum output voltage capacity |
May. 21, 1996 |
| 5448180 |
Transmitter end stage |
Sep. 5, 1995 |
| 5438281 |
Semiconductor integrated circuit device and data processing system having an interface with reduced parasitic capacitance |
Aug. 1, 1995 |
| 5436573 |
High-speed semiconductor integrated circuit device with reduced delay in gate-to-gate wiring |
Jul. 25, 1995 |
| 5436576 |
Switch matrices using reduced number of switching devices for signal routing |
Jul. 25, 1995 |
| 5420524 |
Differential gain stage for use in a standard bipolar ECL process |
May. 30, 1995 |
| 5399918 |
Large fan-in, dynamic, bicmos logic gate |
Mar. 21, 1995 |
| 5187391 |
Modified non-threshold logic circuit |
Feb. 16, 1993 |
| 5160857 |
Integratable transistor switch unit of the NTL logic family |
Nov. 3, 1992 |
| 5153458 |
Code setting circuit with fusible thin film resistors |
Oct. 6, 1992 |
| 5103118 |
High speed anti-undershoot and anti-overshoot circuit |
Apr. 7, 1992 |
| 5091661 |
Methods and apparatus for reducing coupling noise in programmable logic devices |
Feb. 25, 1992 |
| 5065051 |
ECL-TTL level converting circuit |
Nov. 12, 1991 |
| 5049763 |
Anti-noise circuits |
Sep. 17, 1991 |
| 5038327 |
Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors |
Aug. 6, 1991 |
| 5028818 |
Ground bounce limiting driver using non-linear capacitor |
Jul. 2, 1991 |
| 5017808 |
BI-MOS logic circuit having a switch circuit for discharging electrical charge accumulated in a parasitic capacitor |
May. 21, 1991 |
| 5015880 |
CMOS driver circuit |
May. 14, 1991 |
| 5013940 |
Multi stage slew control for an IC output circuit |
May. 7, 1991 |
| 5010260 |
Integrated circuit furnishing a segmented input circuit |
Apr. 23, 1991 |
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