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Class Information
Number: 326/122
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Complementary fet`s
Description: Subject matter wherein the logic function unit includes at least two field-effect transistor elements, each having a channel of conductivity type opposite that of the other (e.g., p-channel vs. n-channel, etc.).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7602219 |
Inverting cell |
Oct. 13, 2009 |
| 7598802 |
Semiconductor integrated circuit apparatus and electronic apparatus |
Oct. 6, 2009 |
| 7592842 |
Configurable delay chain with stacked inverter delay elements |
Sep. 22, 2009 |
| 7417468 |
Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis |
Aug. 26, 2008 |
| 7345511 |
Logic circuit and method of logic circuit design |
Mar. 18, 2008 |
| 7310008 |
Configurable delay chain with stacked inverter delay elements |
Dec. 18, 2007 |
| 7265574 |
Fail-safe method and circuit |
Sep. 4, 2007 |
| 7106093 |
Semiconductor device |
Sep. 12, 2006 |
| 6937538 |
Asynchronously resettable decoder for a semiconductor memory |
Aug. 30, 2005 |
| 6768340 |
Fault-tolerant inverter circuit |
Jul. 27, 2004 |
| 6753695 |
Semiconductor integrated circuit device and pulse width changing circuit |
Jun. 22, 2004 |
| 6744297 |
Inverter circuit |
Jun. 1, 2004 |
| 6714059 |
High-speed domino logic circuit |
Mar. 30, 2004 |
| 6683475 |
High speed digital signal buffer and method |
Jan. 27, 2004 |
| 6373291 |
Pass transistor logic circuit for reducing power consumption |
Apr. 16, 2002 |
| 6329845 |
Logic gate cell |
Dec. 11, 2001 |
| 6252427 |
CMOS inverter and standard cell using the same |
Jun. 26, 2001 |
| 6150848 |
Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication |
Nov. 21, 2000 |
| 5926038 |
Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication |
Jul. 20, 1999 |
| RE35764 |
Inverting output driver circuit for reducing electron injection into the substrate |
Apr. 7, 1998 |
| 5612638 |
Time multiplexed ratioed logic |
Mar. 18, 1997 |
| 5594371 |
Low voltage SOI (Silicon On Insulator) logic circuit |
Jan. 14, 1997 |
| 5508640 |
Dynamic CMOS logic circuit with precharge |
Apr. 16, 1996 |
| 5397940 |
Buffer system with reduced interference |
Mar. 14, 1995 |
| 5373203 |
Decoder and latching circuit with differential outputs |
Dec. 13, 1994 |
| 5367206 |
Output buffer circuit for a low voltage EPROM |
Nov. 22, 1994 |
| 5367210 |
Output buffer with reduced noise |
Nov. 22, 1994 |
| 5361006 |
Electrical circuitry with threshold control |
Nov. 1, 1994 |
| 5355031 |
Complementary logic with n-channel output transistors |
Oct. 11, 1994 |
| 5347179 |
Inverting output driver circuit for reducing electron injection into the substrate |
Sep. 13, 1994 |
| 5347177 |
System for interconnecting VLSI circuits with transmission line characteristics |
Sep. 13, 1994 |
| 5347178 |
CMOS semiconductor logic circuit with multiple input gates |
Sep. 13, 1994 |
| 5331224 |
I.sub.cct leakage current interrupter |
Jul. 19, 1994 |
| 5331220 |
Soft wakeup output buffer |
Jul. 19, 1994 |
| 5331228 |
Output driver circuit |
Jul. 19, 1994 |
| 5247212 |
Complementary logic input parallel (CLIP) logic circuit family |
Sep. 21, 1993 |
| 5068553 |
Delay stage with reduced V.sub.dd dependence |
Nov. 26, 1991 |
| 4859880 |
High speed CMOS differential driver |
Aug. 22, 1989 |
| 4654548 |
Complementary logic circuit |
Mar. 31, 1987 |
| 4103183 |
Quasi-static inverter circuit |
Jul. 25, 1978 |
| 4053792 |
Low power complementary field effect transistor (CFET) logic circuit |
Oct. 11, 1977 |
| 3999081 |
Clock-controlled gate circuit |
Dec. 21, 1976 |
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