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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5939932 |
High-output voltage generating circuit for channel breakdown prevention |
Aug. 17, 1999 |
| 5939900 |
Input buffer |
Aug. 17, 1999 |
| 5939897 |
Method and apparatus for testing quiescent current in integrated circuits |
Aug. 17, 1999 |
| 5923189 |
Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections |
Jul. 13, 1999 |
| 5923184 |
Ferroelectric transistor logic functions for programming |
Jul. 13, 1999 |
| 5909127 |
Circuits with dynamically biased active loads |
Jun. 1, 1999 |
| 5903169 |
Charge recycling differential logic (CRDL) circuit and storage elements and devices using the same |
May. 11, 1999 |
| 5903043 |
Semiconductor device and an arithmetic and logic unit, a signal converter and a signal processing system using the same |
May. 11, 1999 |
| 5900750 |
5V output driver on 2.5V technology |
May. 4, 1999 |
| 5898320 |
Programmable interconnect point having reduced crowbar current |
Apr. 27, 1999 |
| 5896046 |
Latch structure for ripple domino logic |
Apr. 20, 1999 |
| 5892372 |
Creating inversions in ripple domino logic |
Apr. 6, 1999 |
| 5890100 |
Chip temperature monitor using delay lines |
Mar. 30, 1999 |
| 5889416 |
Symmetrical nand gates |
Mar. 30, 1999 |
| 5880604 |
Semiconductor integrated circuit device having power reduction mechanism |
Mar. 9, 1999 |
| 5880608 |
Pulsed domino latches |
Mar. 9, 1999 |
| 5874836 |
High reliability I/O stacked fets |
Feb. 23, 1999 |
| 5861762 |
Inverse toggle XOR and XNOR circuit |
Jan. 19, 1999 |
| 5859547 |
Dynamic logic circuit |
Jan. 12, 1999 |
| 5852373 |
Static-dynamic logic circuit |
Dec. 22, 1998 |
| 5847576 |
Low power, variable logic threshold voltage, logic gates |
Dec. 8, 1998 |
| 5831453 |
Method and apparatus for low power data transmission |
Nov. 3, 1998 |
| 5831452 |
Leak tolerant low power dynamic circuits |
Nov. 3, 1998 |
| 5831450 |
System for improved response time output buffer unit having individual stages for signal generation and buffering and output stage applying signal determined by input signal |
Nov. 3, 1998 |
| 5828236 |
Selectable inverter circuit |
Oct. 27, 1998 |
| 5828235 |
Semiconductor integrated circuit device having power reduction mechanism |
Oct. 27, 1998 |
| 5821769 |
Low voltage CMOS logic circuit with threshold voltage control |
Oct. 13, 1998 |
| 5821775 |
Method and apparatus to interface monotonic and non-monotonic domino logic |
Oct. 13, 1998 |
| 5815007 |
More-than-one detector |
Sep. 29, 1998 |
| 5808483 |
Logic circuit utilizing pass transistors and logic gate |
Sep. 15, 1998 |
| 5804989 |
Logic circuit for a semiconductor memory device |
Sep. 8, 1998 |
| 5793228 |
Noise-tolerant dynamic circuits |
Aug. 11, 1998 |
| 5777491 |
High-performance differential cascode voltage switch with pass gate logic elements |
Jul. 7, 1998 |
| 5764085 |
Method and apparatus for sharing a fet between a plurality of operationally exclusive logic gates |
Jun. 9, 1998 |
| 5751651 |
Semiconductor integrated circuit device having a hierarchical power source configuration |
May. 12, 1998 |
| 5742187 |
Decoder with reduced architecture |
Apr. 21, 1998 |
| 5729155 |
High voltage CMOS circuit which protects the gate oxides from excessive voltages |
Mar. 17, 1998 |
| 5721516 |
CMOS inverter |
Feb. 24, 1998 |
| 5717343 |
High-drive CMOS output buffer with noise supression using pulsed drivers and neighbor-sensing |
Feb. 10, 1998 |
| 5714904 |
High speed serial link for fully duplexed data communication |
Feb. 3, 1998 |
| 5710516 |
Input logic signal buffer circuits |
Jan. 20, 1998 |
| 5701095 |
High speed, low noise CMOS multiplexer with precharge |
Dec. 23, 1997 |
| 5694055 |
Zero static power programmable logic cell |
Dec. 2, 1997 |
| 5689198 |
Circuitry and method for gating information |
Nov. 18, 1997 |
| 5682110 |
Low capacitance bus driver |
Oct. 28, 1997 |
| 5677641 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them |
Oct. 14, 1997 |
| 5675263 |
Hot-clock adiabatic gate using multiple clock signals with different phases |
Oct. 7, 1997 |
| 5675264 |
Phase differential circuit having high synchronicity |
Oct. 7, 1997 |
| 5670898 |
Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance |
Sep. 23, 1997 |
| 5661411 |
Feedback controlled load logic circuit |
Aug. 26, 1997 |
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