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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6064228 |
Circuit configuration for generating digital signals |
May. 16, 2000 |
| 6064234 |
Logic circuit |
May. 16, 2000 |
| 6064233 |
Semiconductor integrated circuit measuring current to test damaged transistor |
May. 16, 2000 |
| 6060909 |
Compound domino logic circuit including an output driver section with a latch |
May. 9, 2000 |
| 6060906 |
Bidirectional buffer with active pull-up/latch circuit for mixed-voltage applications |
May. 9, 2000 |
| 6060904 |
Level shifter circuit certainly operable although a power supply voltage is a low voltage |
May. 9, 2000 |
| 6060911 |
Circuit arrangement with at least four transistors, and method for the manufacture thereof |
May. 9, 2000 |
| 6060910 |
Dynamic logic circuit |
May. 9, 2000 |
| 6054875 |
Output buffer for a mixed voltage environment |
Apr. 25, 2000 |
| 6049232 |
Semiconductor integrated circuit |
Apr. 11, 2000 |
| 6049230 |
Silicon on insulator domino logic circuits |
Apr. 11, 2000 |
| 6046608 |
Differential precharge circuit |
Apr. 4, 2000 |
| 6046606 |
Soft error protected dynamic circuit |
Apr. 4, 2000 |
| 6046604 |
Semiconductor integrated circuit device having power reduction mechanism |
Apr. 4, 2000 |
| 6040717 |
FRCPG: Forecasted restoration complementary pass gates |
Mar. 21, 2000 |
| 6040716 |
Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage |
Mar. 21, 2000 |
| 6037804 |
Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs |
Mar. 14, 2000 |
| 6031394 |
Low voltage CMOS circuit for on/off chip drive at high voltage |
Feb. 29, 2000 |
| 6025739 |
CMOS driver circuit for providing a logic function while reducing pass-through current |
Feb. 15, 2000 |
| 6020763 |
High speed decoder without race condition |
Feb. 1, 2000 |
| 6018253 |
Register with current-steering input network |
Jan. 25, 2000 |
| 6018252 |
Dual-power type integrated circuit |
Jan. 25, 2000 |
| 6018255 |
Line decoder for memory devices |
Jan. 25, 2000 |
| 6016064 |
Interpolating circuit |
Jan. 18, 2000 |
| 6016065 |
Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same |
Jan. 18, 2000 |
| 6014041 |
Differential current switch logic gate |
Jan. 11, 2000 |
| 6011410 |
Method of charging a dynamic node |
Jan. 4, 2000 |
| 6011411 |
CMOS logic circuit with reduced circuit area |
Jan. 4, 2000 |
| 6011409 |
Input/output buffer capable of accepting an input logic signal higher in voltage level than the system voltage |
Jan. 4, 2000 |
| 6009021 |
MOS logic circuit with hold operation |
Dec. 28, 1999 |
| 6008670 |
Differential CMOS logic family |
Dec. 28, 1999 |
| 6005417 |
Method and apparatus for reducing power consumption in a domino logic by reducing unnecessary toggles |
Dec. 21, 1999 |
| 6005416 |
Compiled self-resetting CMOS logic array macros |
Dec. 21, 1999 |
| 6005418 |
Low power consuming logic circuit |
Dec. 21, 1999 |
| 6002272 |
Tri-rail domino circuit |
Dec. 14, 1999 |
| 6002271 |
Dynamic MOS logic circuit without charge sharing noise |
Dec. 14, 1999 |
| 5999018 |
Programmable buffer circuit comprising reduced number of transistors |
Dec. 7, 1999 |
| 5994925 |
Pseudo-differential logic receiver |
Nov. 30, 1999 |
| 5990523 |
Circuit structure which avoids latchup effect |
Nov. 23, 1999 |
| 5990706 |
Logic circuit and method of designing the same |
Nov. 23, 1999 |
| 5986480 |
Multiple input zero power AND/NOR gate for use in a field programmable gate array (FPGA) |
Nov. 16, 1999 |
| 5986478 |
Logical circuit capable of uniformizing output delays for different inputs |
Nov. 16, 1999 |
| 5986476 |
Method and apparatus for implementing a dynamic adiabatic logic family |
Nov. 16, 1999 |
| 5982199 |
Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance |
Nov. 9, 1999 |
| 5977800 |
Differential MOS current-mode logic circuit having high gain and fast speed |
Nov. 2, 1999 |
| 5977789 |
Fast-switching logic gate |
Nov. 2, 1999 |
| 5973514 |
1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation |
Oct. 26, 1999 |
| 5955898 |
Selector and decision wait using pass gate XOR |
Sep. 21, 1999 |
| 5955893 |
Power saving buffer circuit buffer bias voltages |
Sep. 21, 1999 |
| 5942917 |
High speed ratioed CMOS logic structures for a pulsed input environment |
Aug. 24, 1999 |
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