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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6169419 |
Method and apparatus for reducing standby leakage current using a transistor stack effect |
Jan. 2, 2001 |
| 6166561 |
Method and apparatus for protecting off chip driver circuitry employing a split rail power supply |
Dec. 26, 2000 |
| 6163171 |
Pull-up and pull-down circuit |
Dec. 19, 2000 |
| 6163173 |
Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance |
Dec. 19, 2000 |
| 6154062 |
Semiconductor integrated circuits with power reduction mechanism |
Nov. 28, 2000 |
| 6150834 |
Elimination of SOI parasitic bipolar effect |
Nov. 21, 2000 |
| 6150844 |
High voltage tolerance output stage |
Nov. 21, 2000 |
| 6147534 |
Dynamic set/reset circuit with dual feedback |
Nov. 14, 2000 |
| 6147508 |
Power consumption control mechanism and method therefor |
Nov. 14, 2000 |
| 6144228 |
Generalized push-pull cascode logic technique |
Nov. 7, 2000 |
| 6140836 |
Self-timed pipelined datapath system and asynchronous signal control circuit |
Oct. 31, 2000 |
| 6133759 |
Decoupled reset dynamic logic circuit |
Oct. 17, 2000 |
| 6133749 |
Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance |
Oct. 17, 2000 |
| 6133754 |
Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC) |
Oct. 17, 2000 |
| 6130559 |
QMOS digital logic circuits |
Oct. 10, 2000 |
| 6124737 |
Low power clock buffer having a reduced, clocked, pull-down transistor |
Sep. 26, 2000 |
| 6124735 |
Method and apparatus for a N-nary logic circuit using capacitance isolation |
Sep. 26, 2000 |
| 6121796 |
Power-saving dynamic circuit |
Sep. 19, 2000 |
| 6121793 |
Logic device |
Sep. 19, 2000 |
| 6118301 |
High voltage tolerant and compliant driver circuit |
Sep. 12, 2000 |
| 6114872 |
Differential input circuit |
Sep. 5, 2000 |
| 6111434 |
Circuit having anti-charge share characteristics and method therefore |
Aug. 29, 2000 |
| 6111430 |
Circuit for interfacing a first type of logic circuit with a second type of logic circuit |
Aug. 29, 2000 |
| 6111427 |
Logic circuit having different threshold voltage transistors and its fabrication method |
Aug. 29, 2000 |
| 6111435 |
Low power multiplexer with shared, clocked transistor |
Aug. 29, 2000 |
| 6104214 |
Current mode logic circuit, source follower circuit, and flip flop circuit |
Aug. 15, 2000 |
| 6100720 |
Low dissipation inverter circuit |
Aug. 8, 2000 |
| 6100718 |
Circuit for transmitting digital signals |
Aug. 8, 2000 |
| 6099576 |
System for designing and manufacturing CMOS inverters by estimating gate RC delay |
Aug. 8, 2000 |
| 6097215 |
Low power voltage translation circuit |
Aug. 1, 2000 |
| 6097220 |
Method and circuit for recycling charge |
Aug. 1, 2000 |
| 6097222 |
Symmetrical NOR gates |
Aug. 1, 2000 |
| 6097221 |
Semiconductor integrated circuit capable of realizing logic functions |
Aug. 1, 2000 |
| 6094071 |
Initialization of floating body dynamic circuitry |
Jul. 25, 2000 |
| 6094068 |
CMOS logic circuit and method of driving the same |
Jul. 25, 2000 |
| 6090153 |
Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits |
Jul. 18, 2000 |
| 6091656 |
Semiconductor integrated circuit device having a hierarchical power source configuration |
Jul. 18, 2000 |
| 6091265 |
Low voltage CMOS input buffer with undershoot/overshoot protection |
Jul. 18, 2000 |
| 6091264 |
Schmitt trigger input stage |
Jul. 18, 2000 |
| 6087854 |
High speed line driver with direct and complementary outputs |
Jul. 11, 2000 |
| 6087849 |
Soft error immunity in CMOS circuits with large shared diffusion areas |
Jul. 11, 2000 |
| 6084437 |
Logic circuit utilizing pass transistors and logic gate |
Jul. 4, 2000 |
| 6081135 |
Device and method to reduce power consumption in integrated semiconductor devices |
Jun. 27, 2000 |
| 6078195 |
Logic blocks with mixed low and regular V.sub.t MOSFET devices for VLSI design in the deep sub-micron regime |
Jun. 20, 2000 |
| 6078196 |
Data enabled logic circuits |
Jun. 20, 2000 |
| 6075386 |
Dynamic logic gate with relaxed timing requirements and output state holding |
Jun. 13, 2000 |
| 6075382 |
Buffer for integrated circuit pads |
Jun. 13, 2000 |
| 6072335 |
Inverter control circuit |
Jun. 6, 2000 |
| 6069495 |
High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches |
May. 30, 2000 |
| 6066963 |
MOS output driver, and circuit and method of controlling same |
May. 23, 2000 |
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