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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6469541 |
Exclusive Or/Nor circuit |
Oct. 22, 2002 |
| 6469953 |
Latch circuit |
Oct. 22, 2002 |
| 6466057 |
Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method |
Oct. 15, 2002 |
| 6459304 |
Latching annihilation based logic gate |
Oct. 1, 2002 |
| 6456112 |
Method and apparatus for improving signal noise immunity in CMOS dynamic logic circuitry |
Sep. 24, 2002 |
| 6448814 |
CMOS buffer circuit |
Sep. 10, 2002 |
| 6448812 |
Pull up/pull down logic for holding a defined value during power down mode |
Sep. 10, 2002 |
| 6437602 |
Fully dynamic logic network circuits |
Aug. 20, 2002 |
| 6433588 |
Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit |
Aug. 13, 2002 |
| 6433620 |
Silicon-on-insulator CMOS circuit |
Aug. 13, 2002 |
| 6433582 |
Voltage level shifter circuit |
Aug. 13, 2002 |
| 6433585 |
Overvoltage-tolerant interface for integrated circuits |
Aug. 13, 2002 |
| 6429687 |
Semiconductor integrated circuit device |
Aug. 6, 2002 |
| 6426652 |
Dual-edge triggered dynamic logic |
Jul. 30, 2002 |
| 6424176 |
Logic circuits used for address decoding |
Jul. 23, 2002 |
| 6424174 |
Low leakage logic gates |
Jul. 23, 2002 |
| 6420904 |
Domino logic with self-timed precharge |
Jul. 16, 2002 |
| 6420907 |
Method and apparatus for asynchronously controlling state information within a circuit |
Jul. 16, 2002 |
| 6407587 |
Adiabatic logic circuit |
Jun. 18, 2002 |
| 6404239 |
Semiconductor integrated circuit device having power reduction mechanism |
Jun. 11, 2002 |
| 6404233 |
Method and apparatus for logic circuit transition detection |
Jun. 11, 2002 |
| 6396305 |
Digital leakage compensation circuit |
May. 28, 2002 |
| 6396306 |
Regenerative tie-high tie-low cell |
May. 28, 2002 |
| 6396307 |
Semiconductor integrated circuit and method for designing the same |
May. 28, 2002 |
| 6388474 |
Semiconductor integrated circuit |
May. 14, 2002 |
| 6377080 |
Dynamic logic circuit |
Apr. 23, 2002 |
| 6373292 |
Low voltage differential logic |
Apr. 16, 2002 |
| 6369606 |
Mixed threshold voltage CMOS logic device and method of manufacture therefor |
Apr. 9, 2002 |
| 6369616 |
Low power clock buffer with shared, precharge transistor |
Apr. 9, 2002 |
| 6369615 |
Semiconductor integrated circuit and pulse signal generating method |
Apr. 9, 2002 |
| 6366134 |
CMOS dynamic logic circuitry using quantum mechanical tunneling structures |
Apr. 2, 2002 |
| 6366132 |
Soft error resistant circuits |
Apr. 2, 2002 |
| 6366133 |
Logic circuit |
Apr. 2, 2002 |
| 6362659 |
Domino logic family |
Mar. 26, 2002 |
| 6359472 |
Semiconductor integrated circuit and its fabrication method |
Mar. 19, 2002 |
| 6356112 |
Exclusive or/nor circuit |
Mar. 12, 2002 |
| 6356119 |
Semiconductor integrated circuit device having power reduction mechanism |
Mar. 12, 2002 |
| 6353340 |
Input and output circuit with reduced skew between differential signals |
Mar. 5, 2002 |
| 6348815 |
Input buffer circuit |
Feb. 19, 2002 |
| 6344759 |
Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation |
Feb. 5, 2002 |
| 6339344 |
Semiconductor integrated circuit device |
Jan. 15, 2002 |
| 6337584 |
Method and apparatus for reducing bipolar current effects in silicon-on-insulator (SOI) dynamic logic circuits |
Jan. 8, 2002 |
| 6329846 |
Cross-coupled dual rail dynamic logic circuit |
Dec. 11, 2001 |
| 6329867 |
Clock input buffer with noise suppression |
Dec. 11, 2001 |
| 6330182 |
Method for evaluating soft error immunity of CMOS circuits |
Dec. 11, 2001 |
| 6329845 |
Logic gate cell |
Dec. 11, 2001 |
| 6326814 |
Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates |
Dec. 4, 2001 |
| 6323691 |
Logic circuit |
Nov. 27, 2001 |
| 6313666 |
Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit |
Nov. 6, 2001 |
| 6300801 |
Or gate circuit and state machine using the same |
Oct. 9, 2001 |
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