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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7292061 |
Semiconductor integrated circuit having current leakage reduction scheme |
Nov. 6, 2007 |
| 7292064 |
Minimizing timing skew among chip level outputs for registered output signals |
Nov. 6, 2007 |
| 7288968 |
Circuit element |
Oct. 30, 2007 |
| 7282959 |
CMOS circuit including double-insulated-gate field-effect transistors |
Oct. 16, 2007 |
| 7282960 |
Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock |
Oct. 16, 2007 |
| 7282961 |
Apparatus for hysteresis based process compensation for CMOS receiver circuits |
Oct. 16, 2007 |
| 7274216 |
Duty cycle controlled CML-CMOS converter |
Sep. 25, 2007 |
| 7265574 |
Fail-safe method and circuit |
Sep. 4, 2007 |
| 7265589 |
Independent gate control logic circuitry |
Sep. 4, 2007 |
| 7259590 |
Driver for multi-voltage island/core architecture |
Aug. 21, 2007 |
| 7256622 |
AND, OR, NAND, and NOR logical gates |
Aug. 14, 2007 |
| 7256621 |
Keeper circuits having dynamic leakage compensation |
Aug. 14, 2007 |
| 7256619 |
Apparatus to shift to pre-charge mode a dynamic circuit driven by one-shot clock signal during power off mode |
Aug. 14, 2007 |
| 7253663 |
Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications |
Aug. 7, 2007 |
| 7221189 |
Dynamic node keeper system and method |
May. 22, 2007 |
| 7218153 |
Word line driver with reduced leakage current |
May. 15, 2007 |
| 7202700 |
Semiconductor device which exhibits high-speed performance and low power consumption |
Apr. 10, 2007 |
| 7202704 |
Leakage sensing and keeper circuit for proper operation of a dynamic circuit |
Apr. 10, 2007 |
| 7193445 |
Non-inverting domino register |
Mar. 20, 2007 |
| 7187209 |
Non-inverting domino register |
Mar. 6, 2007 |
| 7161390 |
Dynamic latching logic structure with static interfaces for implementing improved data setup time |
Jan. 9, 2007 |
| 7161389 |
Ratioed logic circuits with contention interrupt |
Jan. 9, 2007 |
| 7157941 |
Differential switching circuit and digital-to-analog converter |
Jan. 2, 2007 |
| 7138833 |
Selector circuit |
Nov. 21, 2006 |
| 7138835 |
Method and apparatus for an equalizing buffer |
Nov. 21, 2006 |
| 7129756 |
Semiconductor integrated circuit |
Oct. 31, 2006 |
| 7106093 |
Semiconductor device |
Sep. 12, 2006 |
| 7095252 |
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates |
Aug. 22, 2006 |
| 7088144 |
Conditional precharge design in staticized dynamic flip-flop with clock enable |
Aug. 8, 2006 |
| 7088145 |
AC powered logic circuitry |
Aug. 8, 2006 |
| 7088143 |
Dynamic circuits having improved noise tolerance and method for designing same |
Aug. 8, 2006 |
| 7075337 |
Single event upset immune keeper circuit and method for dual redundant dynamic logic |
Jul. 11, 2006 |
| 7071758 |
Voltage level shifter |
Jul. 4, 2006 |
| 7068077 |
LVDS output driver having low supply voltage capability |
Jun. 27, 2006 |
| 7064584 |
P-domino output latch with accelerated evaluate path |
Jun. 20, 2006 |
| 7053665 |
Circuits and methods for high-capacity asynchronous pipeline processing |
May. 30, 2006 |
| 7053663 |
Dynamic gate with conditional keeper for soft error rate reduction |
May. 30, 2006 |
| 7053664 |
Null value propagation for FAST14 logic |
May. 30, 2006 |
| 7034578 |
N-domino output latch with accelerated evaluate path |
Apr. 25, 2006 |
| 7015723 |
Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation |
Mar. 21, 2006 |
| 7009425 |
Methods and apparatus for improving large signal performance for active shunt-peaked circuits |
Mar. 7, 2006 |
| 7002371 |
Level shifter |
Feb. 21, 2006 |
| 6977528 |
Event driven dynamic logic for reducing power consumption |
Dec. 20, 2005 |
| 6978387 |
Hold time latch with decreased percharge node voltage leakage |
Dec. 20, 2005 |
| 6975143 |
Static logic design for CMOS |
Dec. 13, 2005 |
| 6970019 |
Semiconductor integrated circuit device having power reduction mechanism |
Nov. 29, 2005 |
| 6967381 |
Semiconductor device |
Nov. 22, 2005 |
| 6958623 |
Three terminal noninverting transistor switch |
Oct. 25, 2005 |
| 6958628 |
Three-transistor NAND and NOR gates for two-phase clock generators |
Oct. 25, 2005 |
| 6956406 |
Static storage element for dynamic logic |
Oct. 18, 2005 |
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