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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5359239 |
Output circuit with reduced switching noise |
Oct. 25, 1994 |
| 5359243 |
Fast TTL to CMOS level converting buffer with low standby power |
Oct. 25, 1994 |
| 5359240 |
Low power digital signal buffer circuit |
Oct. 25, 1994 |
| 5355028 |
Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators |
Oct. 11, 1994 |
| 5351217 |
Word line voltage supply circuit |
Sep. 27, 1994 |
| 5349246 |
Input buffer with hysteresis characteristics |
Sep. 20, 1994 |
| 5343090 |
Speed enhancement technique for CMOS circuits |
Aug. 30, 1994 |
| 5332934 |
Small to full swing conversion circuit |
Jul. 26, 1994 |
| 5329177 |
Output circuit including current mirror circuits |
Jul. 12, 1994 |
| 5329186 |
CMOS bootstrapped output driver method and circuit |
Jul. 12, 1994 |
| 5329185 |
CMOS logic circuitry providing improved operating speed |
Jul. 12, 1994 |
| 5327020 |
Schmitt trigger input buffer circuit |
Jul. 5, 1994 |
| 5319260 |
Apparatus and method to prevent the disturbance of a quiescent output buffer caused by ground bounce or by power bounce induced by neighboring active output buffers |
Jun. 7, 1994 |
| 5311073 |
High voltage CMOS circuit with NAND configured logic gates and a reduced number of N-MOS transistors requiring drain extension |
May. 10, 1994 |
| 5311070 |
Seu-immune latch for gate array, standard cell, and other asic applications |
May. 10, 1994 |
| 5311082 |
CMOS to ECL level translator |
May. 10, 1994 |
| 5311075 |
Level shifting CMOS integrated circuits |
May. 10, 1994 |
| 5309043 |
Compound logic circuit having NAND and NOR gate outputs and two transistors connected within both gate circuits |
May. 3, 1994 |
| 5300835 |
CMOS low power mixed voltage bidirectional I/O buffer |
Apr. 5, 1994 |
| 5298807 |
Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry |
Mar. 29, 1994 |
| 5298804 |
Output circuit which surpresses ringing |
Mar. 29, 1994 |
| 5296757 |
Low-noise output driver having separate supply lines and sequenced operation for transient and steady-state portions |
Mar. 22, 1994 |
| 5296766 |
CMOS circuit with crowbar limiting function |
Mar. 22, 1994 |
| 5296758 |
Output buffer with ground bounce compensation |
Mar. 22, 1994 |
| 5293082 |
Output driver for reducing transient noise in integrated circuits |
Mar. 8, 1994 |
| 5283631 |
Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations |
Feb. 1, 1994 |
| 5281869 |
Reduced-voltage NMOS output driver |
Jan. 25, 1994 |
| 5281870 |
Current controller |
Jan. 25, 1994 |
| 5280201 |
Semiconductor logic circuit apparatus |
Jan. 18, 1994 |
| 5280200 |
Pipelined buffer for analog signal and power supply |
Jan. 18, 1994 |
| 5278460 |
Voltage compensating CMOS input buffer |
Jan. 11, 1994 |
| 5276366 |
Digital voltage level translator circuit |
Jan. 4, 1994 |
| 5274284 |
Output buffer circuits with controlled Miller effect capacitance |
Dec. 28, 1993 |
| 5274282 |
Monostabilized dynamic programmable logic array in CMOS technology |
Dec. 28, 1993 |
| 5274276 |
Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit |
Dec. 28, 1993 |
| 5274279 |
Thin film CMOS inverter |
Dec. 28, 1993 |
| 5270587 |
CMOS logic cell for high-speed, zero-power programmable array logic devices |
Dec. 14, 1993 |
| 5268599 |
TTL to CMOS input buffer using CMOS structure |
Dec. 7, 1993 |
| 5264741 |
Low current, fast, CMOS static pullup circuit for static random-access memories |
Nov. 23, 1993 |
| 5263173 |
High speed clocked output driver for switching logic levels of an output pad at integer and integer and a half clock cycles |
Nov. 16, 1993 |
| 5258663 |
Reference voltage generating circuit having reduced power consumption |
Nov. 2, 1993 |
| 5250855 |
Fast logic circuits |
Oct. 5, 1993 |
| 5241221 |
CMOS driver circuit having reduced switching noise |
Aug. 31, 1993 |
| 5239208 |
Constant current circuit employing transistors having specific gate dimensions |
Aug. 24, 1993 |
| 5227679 |
Cmos digital-controlled delay gate |
Jul. 13, 1993 |
| 5216289 |
Asynchronous reset scheme for ultra-low noise port tri-state output driver circuit |
Jun. 1, 1993 |
| 5208490 |
Functionally complete family of self-timed dynamic logic circuits |
May. 4, 1993 |
| 5208489 |
Multiple compound domino logic circuit |
May. 4, 1993 |
| 5208488 |
Potential detecting circuit |
May. 4, 1993 |
| 5200653 |
Tristate output gate structure particularly for CMOS integrated circuits |
Apr. 6, 1993 |
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