 |
|
 |
| |
 |
|
Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5654652 |
High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback |
Aug. 5, 1997 |
| 5654651 |
CMOS static logic circuit |
Aug. 5, 1997 |
| 5646550 |
High reliability output buffer for multiple voltage system |
Jul. 8, 1997 |
| 5640105 |
Current mode null convention threshold gate |
Jun. 17, 1997 |
| 5629638 |
Adaptive threshold voltage CMOS circuits |
May. 13, 1997 |
| 5614847 |
Semiconductor integrated circuit device having power reduction mechanism |
Mar. 25, 1997 |
| 5612638 |
Time multiplexed ratioed logic |
Mar. 18, 1997 |
| 5610537 |
Trinary logic input gate |
Mar. 11, 1997 |
| 5608340 |
Four-terminal semiconductor device |
Mar. 4, 1997 |
| 5606270 |
Dynamic clocked inverter latch with reduced charge leakage |
Feb. 25, 1997 |
| 5604449 |
Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes |
Feb. 18, 1997 |
| 5598106 |
Semiconductor integrated circuit for preventing deterioration of the characteristics of an N-channel type transistor |
Jan. 28, 1997 |
| 5594372 |
Source follower using NMOS and PMOS transistors |
Jan. 14, 1997 |
| 5594369 |
Open-drain fet output circuit |
Jan. 14, 1997 |
| 5592107 |
Configurable NAND/NOR element |
Jan. 7, 1997 |
| 5585740 |
CMOS low output voltage bus driver with controlled clamps |
Dec. 17, 1996 |
| 5583457 |
Semiconductor integrated circuit device having power reduction mechanism |
Dec. 10, 1996 |
| 5583456 |
Differentially coupled AND/NAND and XOR/XNOR circuitry |
Dec. 10, 1996 |
| 5583460 |
Output driver circuit for restraining generation of noise and semiconductor memory device utilizing such circuit |
Dec. 10, 1996 |
| 5583454 |
Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function |
Dec. 10, 1996 |
| 5568069 |
High speed, low power pipelined logic circuit |
Oct. 22, 1996 |
| 5559453 |
Interlocked restore circuit |
Sep. 24, 1996 |
| 5550486 |
Circuit and method for providing a known logic state at insufficient supply voltage |
Aug. 27, 1996 |
| 5546022 |
Static logic circuit with improved output signal levels |
Aug. 13, 1996 |
| 5541527 |
PECL buffer |
Jul. 30, 1996 |
| 5541528 |
CMOS buffer circuit having increased speed |
Jul. 30, 1996 |
| 5541537 |
High speed static circuit design |
Jul. 30, 1996 |
| 5539335 |
Output buffer circuit for semiconductor device |
Jul. 23, 1996 |
| 5537063 |
CMOS logic circuit with plural inputs |
Jul. 16, 1996 |
| 5534790 |
Current transition rate control circuit |
Jul. 9, 1996 |
| 5532617 |
CMOS input with temperature and V.sub.CC compensated threshold |
Jul. 2, 1996 |
| 5532622 |
Multi-input transition detector with a single delay |
Jul. 2, 1996 |
| 5525916 |
All-N-logic high-speed single-phase dynamic CMOS logic |
Jun. 11, 1996 |
| 5517133 |
Multiple-input OR-gate employing a sense amplifier |
May. 14, 1996 |
| RE35221 |
Schottky enhanced CMOS output circuit |
Apr. 30, 1996 |
| 5508641 |
Integrated circuit chip and pass gate logic family therefor |
Apr. 16, 1996 |
| 5493233 |
MOSFET circuit apparatus with avalanche breakdown prevention means |
Feb. 20, 1996 |
| 5491429 |
Apparatus for reducing current consumption in a CMOS inverter circuit |
Feb. 13, 1996 |
| 5490119 |
Semiconductor device including signal generating circuit with level converting function and with reduced area of occupation |
Feb. 6, 1996 |
| 5483181 |
Dynamic logic circuit with reduced charge leakage |
Jan. 9, 1996 |
| 5479117 |
Hybrid data processing system including pulsed-power-supply CMOS circuits |
Dec. 26, 1995 |
| 5479116 |
Level conversion circuits for converting a digital input signal varying between first and second voltage levels to a digital output signal varying between first and third voltage levels |
Dec. 26, 1995 |
| 5479112 |
Logic gate with matched output rise and fall times and method of construction |
Dec. 26, 1995 |
| 5479107 |
Asynchronous logic circuit for 2-phase operation |
Dec. 26, 1995 |
| 5473263 |
Negative feedback to reduce voltage oscillation in CMOS output buffers |
Dec. 5, 1995 |
| 5471150 |
Buffer with high and low speed input buffers |
Nov. 28, 1995 |
| 5469085 |
Source follower using two pairs of NMOS and PMOS transistors |
Nov. 21, 1995 |
| 5465054 |
High voltage CMOS logic using low voltage CMOS process |
Nov. 7, 1995 |
| 5463330 |
CMOS input circuit |
Oct. 31, 1995 |
| 5463240 |
CMIS device with increased gain |
Oct. 31, 1995 |
|
|
|
 |
|
 |
|
| |
Randomly Featured Patents |
|
