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Class Information
Number: 326/121
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Mosfet (i.e., metal-oxide semiconductor field-effect transistor) > Cmos
Description: Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS vs. N-MOS).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7619448 |
Replica bias circuit for high speed low voltage common mode driver |
Nov. 17, 2009 |
| 7602219 |
Inverting cell |
Oct. 13, 2009 |
| 7598774 |
Reduced power consumption limited-switch dynamic logic (LSDL) circuit |
Oct. 6, 2009 |
| 7592841 |
Circuit configurations having four terminal JFET devices |
Sep. 22, 2009 |
| 7592842 |
Configurable delay chain with stacked inverter delay elements |
Sep. 22, 2009 |
| 7589566 |
Semiconductor device provided with antenna ratio countermeasure circuit |
Sep. 15, 2009 |
| 7579872 |
Low-voltage differential signal driver for high-speed digital transmission |
Aug. 25, 2009 |
| 7576567 |
Low-voltage differential signal driver for high-speed digital transmission |
Aug. 18, 2009 |
| 7576568 |
Self-selecting precharged domino logic circuit |
Aug. 18, 2009 |
| 7570080 |
Set dominant latch with soft error resiliency |
Aug. 4, 2009 |
| 7570081 |
Multiple-output static logic |
Aug. 4, 2009 |
| 7564270 |
Differential output driver |
Jul. 21, 2009 |
| 7560955 |
Logic circuit |
Jul. 14, 2009 |
| 7557616 |
Limited switch dynamic logic cell based register |
Jul. 7, 2009 |
| 7557618 |
Conditioning logic technology |
Jul. 7, 2009 |
| 7541839 |
Semiconductor device having a pseudo power supply wiring |
Jun. 2, 2009 |
| 7528630 |
High speed flip-flop |
May. 5, 2009 |
| 7521762 |
Semiconductor integrated circuit device operating with low power consumption |
Apr. 21, 2009 |
| 7498847 |
Output driver that operates both in a differential mode and in a single mode |
Mar. 3, 2009 |
| 7495477 |
Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications |
Feb. 24, 2009 |
| 7479807 |
Leakage dependent online process variation tolerant technique for internal static storage node |
Jan. 20, 2009 |
| 7471124 |
Chopper circuit that chops edge of control signal |
Dec. 30, 2008 |
| 7463068 |
Apparatus and method for over-voltage, under-voltage and over-current stress protection for transceiver input and output circuitry |
Dec. 9, 2008 |
| 7436212 |
Interface circuit power reduction |
Oct. 14, 2008 |
| 7417465 |
N-domino output latch |
Aug. 26, 2008 |
| 7414436 |
Limited switch dynamic logic cell based register |
Aug. 19, 2008 |
| 7411425 |
Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit |
Aug. 12, 2008 |
| 7388406 |
CML circuit devices having improved headroom |
Jun. 17, 2008 |
| 7389478 |
System and method for designing a low leakage monotonic CMOS logic circuit |
Jun. 17, 2008 |
| 7385426 |
Low current offset integrator with signal independent low input capacitance buffer circuit |
Jun. 10, 2008 |
| 7382162 |
High-density logic techniques with reduced-stack multi-gate field effect transistors |
Jun. 3, 2008 |
| 7382161 |
Accelerated P-channel dynamic register |
Jun. 3, 2008 |
| 7365576 |
Binary digital latches not using only NAND or NOR circuits |
Apr. 29, 2008 |
| 7362140 |
Low swing current mode logic family |
Apr. 22, 2008 |
| 7355455 |
Low power consumption MIS semiconductor device |
Apr. 8, 2008 |
| 7352213 |
Ac powered logic circuitry |
Apr. 1, 2008 |
| 7348806 |
Accelerated N-channel dynamic register |
Mar. 25, 2008 |
| 7342421 |
CMOS circuit arrangement |
Mar. 11, 2008 |
| 7342423 |
Circuit and method for calculating a logical combination of two input operands |
Mar. 11, 2008 |
| 7336105 |
Dual gate transistor keeper dynamic logic |
Feb. 26, 2008 |
| 7336104 |
Multiple-output transistor logic circuit |
Feb. 26, 2008 |
| 7336103 |
Stacked inverter delay chain |
Feb. 26, 2008 |
| 7336102 |
Error correcting logic system |
Feb. 26, 2008 |
| 7332938 |
Domino logic testing systems and methods |
Feb. 19, 2008 |
| 7329931 |
Receiver circuit using nanotube-based switches and transistors |
Feb. 12, 2008 |
| 7330054 |
Leakage efficient anti-glitch filter |
Feb. 12, 2008 |
| 7321243 |
P-domino register with accelerated non-charge path |
Jan. 22, 2008 |
| 7317339 |
N-domino register with accelerated non-discharge path |
Jan. 8, 2008 |
| 7310008 |
Configurable delay chain with stacked inverter delay elements |
Dec. 18, 2007 |
| 7298177 |
Method and mechanism to determine keeper size |
Nov. 20, 2007 |
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