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Class Information
Number: 326/114
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.) > Wired logic (e.g., wired-or, wired-and, dotted logic, etc.)
Description: Subject matter which includes a logic family having their output gates eliminated simply by wiring the outputs of some basic logic circuits together, the resultant circuit is called wired-OR or wired-AND depending on the type of logic, and the joint output is in turn input to other logic gates for performing additional logic functions.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7560955 |
Logic circuit |
Jul. 14, 2009 |
| 7550998 |
Inverter circuit having a feedback switch and methods corresponding thereto |
Jun. 23, 2009 |
| 7456660 |
Semiconductor device and display device |
Nov. 25, 2008 |
| 7394294 |
Complementary pass-transistor logic circuit and semiconductor device |
Jul. 1, 2008 |
| 7342423 |
Circuit and method for calculating a logical combination of two input operands |
Mar. 11, 2008 |
| 7279936 |
Logic basic cell, logic basic cell arrangement and logic device |
Oct. 9, 2007 |
| 7265580 |
Semiconductor-integrated circuit utilizing magnetoresistive effect elements |
Sep. 4, 2007 |
| 7256622 |
AND, OR, NAND, and NOR logical gates |
Aug. 14, 2007 |
| 7203789 |
Architecture and methods for computing with reconfigurable resistor crossbars |
Apr. 10, 2007 |
| 7187207 |
Leakage balancing transistor for jitter reduction in CML to CMOS converters |
Mar. 6, 2007 |
| 7161389 |
Ratioed logic circuits with contention interrupt |
Jan. 9, 2007 |
| 6998877 |
High speed differential signaling logic gate and applications thereof |
Feb. 14, 2006 |
| 6972598 |
Methods and arrangements for an enhanced scanable latch circuit |
Dec. 6, 2005 |
| 6954451 |
Distributed time-multiplexed bus architecture and emulation apparatus |
Oct. 11, 2005 |
| 6891398 |
Skewed falling logic device for rapidly propagating a falling edge of an output signal |
May. 10, 2005 |
| 6820242 |
Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit |
Nov. 16, 2004 |
| 6794902 |
Virtual ground circuit |
Sep. 21, 2004 |
| 6720797 |
Pass transistor circuit with exclusive controls |
Apr. 13, 2004 |
| 6674308 |
Low power wired OR |
Jan. 6, 2004 |
| 6448818 |
Apparatus, method and system for a ratioed NOR logic arrangement |
Sep. 10, 2002 |
| 6433588 |
Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit |
Aug. 13, 2002 |
| 6420906 |
FET-OR circuit and power supply circuit using the same |
Jul. 16, 2002 |
| 6388474 |
Semiconductor integrated circuit |
May. 14, 2002 |
| 6313666 |
Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit |
Nov. 6, 2001 |
| 6310489 |
Method to reduce wire-or glitch in high performance bus design to improve bus performance |
Oct. 30, 2001 |
| 6297669 |
Low-technology inexpensive logic module system |
Oct. 2, 2001 |
| 6262598 |
Voltage level shifter |
Jul. 17, 2001 |
| 6259276 |
Semiconductor integrated circuit |
Jul. 10, 2001 |
| 6239619 |
Method and apparatus for dynamic termination logic of data buses |
May. 29, 2001 |
| 5804990 |
Wired combinational logic circuit with pullup and pulldown devices |
Sep. 8, 1998 |
| 5796128 |
Gate array with fully wired multiplexer circuits |
Aug. 18, 1998 |
| 5701094 |
Logic circuits for wave pipelining |
Dec. 23, 1997 |
| 5621677 |
Method and apparatus for precharging match output in a cascaded content addressable memory system |
Apr. 15, 1997 |
| 5528177 |
Complementary field-effect transistor logic circuits for wave pipelining |
Jun. 18, 1996 |
| 5488317 |
Wired logic functions on FPGA's |
Jan. 30, 1996 |
| 5408146 |
High performance backplane driver circuit |
Apr. 18, 1995 |
| 5243227 |
Fine/coarse wired-or tapped delay line |
Sep. 7, 1993 |
| 5225719 |
Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix |
Jul. 6, 1993 |
| 5223752 |
Level conversion circuit for converting ECL-level signals into mos-level signals and address signal decoding system having the level conversion circuit |
Jun. 29, 1993 |
| 5216292 |
Pullup resistance control input circuit and output circuit |
Jun. 1, 1993 |
| 5208490 |
Functionally complete family of self-timed dynamic logic circuits |
May. 4, 1993 |
| 5192879 |
MOS transistor output circuit |
Mar. 9, 1993 |
| 5162673 |
Bi-CMOS logic circuit |
Nov. 10, 1992 |
| 5153455 |
Transition-based wired "OR" for VLSI systems |
Oct. 6, 1992 |
| 5047673 |
High speed output structure suitable for wired-OR structure |
Sep. 10, 1991 |
| 5030852 |
Quasicomplementary MESFET logic circuit with increased noise imunity |
Jul. 9, 1991 |
| 5027012 |
Programmable logic circuit using wired-or tristate gates |
Jun. 25, 1991 |
| 4899066 |
OR-type CMOS logic circuit with fast precharging |
Feb. 6, 1990 |
| 4894558 |
Power saving input buffer for use with a gate array |
Jan. 16, 1990 |
| 4833650 |
Semiconductor memory device including programmable mode selection circuitry |
May. 23, 1989 |
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