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Class Information
Number: 326/112
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Field-effect transistor (e.g., jfet, etc.)
Description: Subject matter wherein the logic circuit includes a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7619440 |
Circuit having logic state retention during power-down and method therefor |
Nov. 17, 2009 |
| 7592840 |
Domino circuit with disable feature |
Sep. 22, 2009 |
| 7576567 |
Low-voltage differential signal driver for high-speed digital transmission |
Aug. 18, 2009 |
| 7573300 |
Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same |
Aug. 11, 2009 |
| 7560957 |
High-speed CML circuit design |
Jul. 14, 2009 |
| 7560955 |
Logic circuit |
Jul. 14, 2009 |
| 7554364 |
High-voltage operational amplifier input stage and method |
Jun. 30, 2009 |
| 7550992 |
Logic cell with two isolated redundant outputs, and corresponding integrated circuit |
Jun. 23, 2009 |
| 7550998 |
Inverter circuit having a feedback switch and methods corresponding thereto |
Jun. 23, 2009 |
| 7548108 |
Semiconductor integrated circuit device with dual insulation system |
Jun. 16, 2009 |
| 7535260 |
Logic gates, scan drivers and organic light emitting displays using the same |
May. 19, 2009 |
| 7535261 |
Logic circuit |
May. 19, 2009 |
| 7498847 |
Output driver that operates both in a differential mode and in a single mode |
Mar. 3, 2009 |
| 7498833 |
Semiconductor integrated circuit |
Mar. 3, 2009 |
| 7486106 |
CPLD for multi-wire keyboard decode with timed power control circuit |
Feb. 3, 2009 |
| 7479801 |
Power gating techniques able to have data retention and variability immunity properties |
Jan. 20, 2009 |
| 7474125 |
Method of producing and operating a low power junction field effect transistor |
Jan. 6, 2009 |
| 7471114 |
Design structure for a current control mechanism for power networks and dynamic logic keeper circuits |
Dec. 30, 2008 |
| 7471115 |
Error correcting logic system |
Dec. 30, 2008 |
| 7436215 |
Transmitter |
Oct. 14, 2008 |
| 7436212 |
Interface circuit power reduction |
Oct. 14, 2008 |
| 7429880 |
Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) |
Sep. 30, 2008 |
| 7428160 |
Nonvolatile programmable logic circuit |
Sep. 23, 2008 |
| 7420388 |
Power gating techniques able to have data retention and variability immunity properties |
Sep. 2, 2008 |
| 7417469 |
Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper |
Aug. 26, 2008 |
| 7417468 |
Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis |
Aug. 26, 2008 |
| 7403038 |
Semiconductor device and display device |
Jul. 22, 2008 |
| 7397271 |
Semiconductor integrated circuit device |
Jul. 8, 2008 |
| 7394294 |
Complementary pass-transistor logic circuit and semiconductor device |
Jul. 1, 2008 |
| 7394297 |
Logic gate with reduced sub-threshold leak current |
Jul. 1, 2008 |
| 7388406 |
CML circuit devices having improved headroom |
Jun. 17, 2008 |
| 7385441 |
Level shifter with reduced power consumption |
Jun. 10, 2008 |
| 7382162 |
High-density logic techniques with reduced-stack multi-gate field effect transistors |
Jun. 3, 2008 |
| 7375547 |
Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method |
May. 20, 2008 |
| 7365576 |
Binary digital latches not using only NAND or NOR circuits |
Apr. 29, 2008 |
| 7363595 |
Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation |
Apr. 22, 2008 |
| 7345511 |
Logic circuit and method of logic circuit design |
Mar. 18, 2008 |
| 7342423 |
Circuit and method for calculating a logical combination of two input operands |
Mar. 11, 2008 |
| 7336105 |
Dual gate transistor keeper dynamic logic |
Feb. 26, 2008 |
| 7336104 |
Multiple-output transistor logic circuit |
Feb. 26, 2008 |
| 7336102 |
Error correcting logic system |
Feb. 26, 2008 |
| 7312640 |
Semiconductor integrated circuit device having power reduction mechanism |
Dec. 25, 2007 |
| 7307457 |
Apparatus for implementing dynamic data path with interlocked keeper and restore devices |
Dec. 11, 2007 |
| 7301371 |
Transmitter of a semiconductor device |
Nov. 27, 2007 |
| 7298171 |
Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices |
Nov. 20, 2007 |
| 7295042 |
Buffer |
Nov. 13, 2007 |
| 7292064 |
Minimizing timing skew among chip level outputs for registered output signals |
Nov. 6, 2007 |
| 7288970 |
Integrated nanotube and field effect switching device |
Oct. 30, 2007 |
| 7282961 |
Apparatus for hysteresis based process compensation for CMOS receiver circuits |
Oct. 16, 2007 |
| 7282960 |
Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock |
Oct. 16, 2007 |
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