| |
 |
|
Class Information
Number: 326/108
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Decoding > With field-effect transistor > Cmos
Description: Subject matter wherein the logic function unit includes at least two metal-oxide field-effect transistors (MOSFET), each having a channel of conductivity type opposite that of the other (e.g., p-channel vs. n-channel, etc.).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7586334 |
Circuit arrangement and method for processing a dual-rail signal |
Sep. 8, 2009 |
| 7535251 |
Semiconductor device and impedance adjusting method thereof |
May. 19, 2009 |
| 7535259 |
Clocked inverter, NAND, NOR and shift register |
May. 19, 2009 |
| 7486113 |
Decoder circuit |
Feb. 3, 2009 |
| 7456660 |
Semiconductor device and display device |
Nov. 25, 2008 |
| 7423450 |
Techniques for providing calibrated on-chip termination impedance |
Sep. 9, 2008 |
| 7378879 |
Decoding systems and methods |
May. 27, 2008 |
| 7358769 |
XOR circuit |
Apr. 15, 2008 |
| 7327169 |
Clocked inverter, NAND, NOR and shift register |
Feb. 5, 2008 |
| 7279936 |
Logic basic cell, logic basic cell arrangement and logic device |
Oct. 9, 2007 |
| 7181966 |
Physical quantity sensor and method for manufacturing the same |
Feb. 27, 2007 |
| 7109758 |
System and method for reducing short circuit current in a buffer |
Sep. 19, 2006 |
| 7049851 |
Decoder circuit |
May. 23, 2006 |
| 7038486 |
Semiconductor integrated circuit device |
May. 2, 2006 |
| 6995600 |
Fast and wire multiplexing circuits |
Feb. 7, 2006 |
| 6954401 |
Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder |
Oct. 11, 2005 |
| 6937538 |
Asynchronously resettable decoder for a semiconductor memory |
Aug. 30, 2005 |
| 6930534 |
Temperature compensated integrated circuits |
Aug. 16, 2005 |
| 6864721 |
Decoder circuit |
Mar. 8, 2005 |
| 6856173 |
Multiplexing of digital signals at multiple supply voltages in an integrated circuit |
Feb. 15, 2005 |
| 6812736 |
Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time |
Nov. 2, 2004 |
| 6794905 |
CMOS inverter |
Sep. 21, 2004 |
| 6759873 |
Reverse biasing logic circuit |
Jul. 6, 2004 |
| 6724225 |
Logic circuit for true and complement signal generator |
Apr. 20, 2004 |
| 6696864 |
Logic circuit and its forming method |
Feb. 24, 2004 |
| 6646951 |
High performance address decode technique for arrays |
Nov. 11, 2003 |
| 6628145 |
High-speed logic gate |
Sep. 30, 2003 |
| 6600342 |
Column decoder of semiconductor memory device |
Jul. 29, 2003 |
| 6597201 |
Dynamic predecoder circuitry for memory circuits |
Jul. 22, 2003 |
| 6593776 |
Method and apparatus for low power domino decoding |
Jul. 15, 2003 |
| 6586970 |
Address decoder with pseudo and or pseudo nand gate |
Jul. 1, 2003 |
| 6583650 |
Latching annihilation based logic gate |
Jun. 24, 2003 |
| 6489811 |
Logic gate with symmetrical propagation delay from any input to any output and a controlled output pulse width |
Dec. 3, 2002 |
| 6480055 |
Decoder element for generating an output signal having three different potentials and an operating method for the decoder element |
Nov. 12, 2002 |
| 6476644 |
Clocked logic gate circuit |
Nov. 5, 2002 |
| 6459304 |
Latching annihilation based logic gate |
Oct. 1, 2002 |
| 6426655 |
Row decoder with switched power supply |
Jul. 30, 2002 |
| 6411140 |
Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit |
Jun. 25, 2002 |
| 6400183 |
Logic circuit and its forming method |
Jun. 4, 2002 |
| 6396306 |
Regenerative tie-high tie-low cell |
May. 28, 2002 |
| 6369617 |
Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit |
Apr. 9, 2002 |
| 6362658 |
Decoder for memories having optimized configuration |
Mar. 26, 2002 |
| 6323690 |
Logic circuit and its forming method |
Nov. 27, 2001 |
| 6323691 |
Logic circuit |
Nov. 27, 2001 |
| 6278297 |
Row decoder with switched power supply |
Aug. 21, 2001 |
| 6225829 |
device signature generator |
May. 1, 2001 |
| 6195027 |
Capacitive precharging and discharging network for converting N bit input into M bit output |
Feb. 27, 2001 |
| 6172531 |
Low power wordline decoder circuit with minimized hold time |
Jan. 9, 2001 |
| 6163174 |
Digital buffer circuits |
Dec. 19, 2000 |
| 6160752 |
Semiconductor memory device |
Dec. 12, 2000 |
|
|
|
