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Class Information
Number: 326/107
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Decoding > With field-effect transistor > Depletion or enhancement
Description: Subject matter wherein the decoder includes either a depletion type which has channel conductivity on for zero or negative gate-source voltage or an enhancement type which is normally off with zero or negative gate source voltage bias applied.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7164294 |
Method for forming programmable logic arrays using vertical gate transistors |
Jan. 16, 2007 |
| 6864721 |
Decoder circuit |
Mar. 8, 2005 |
| 6759873 |
Reverse biasing logic circuit |
Jul. 6, 2004 |
| 6653998 |
LCD driver for layout and power savings |
Nov. 25, 2003 |
| 6593776 |
Method and apparatus for low power domino decoding |
Jul. 15, 2003 |
| 6496035 |
Integrated circuit approach, with a serpentine conductor track for circuit configuration selection |
Dec. 17, 2002 |
| 6201416 |
Field effect transistor logic circuit with reduced power consumption |
Mar. 13, 2001 |
| 5848013 |
Row decoding circuit for semiconductor non-volatile electrically programmable memory and corresponding method |
Dec. 8, 1998 |
| 5801551 |
Depletion mode pass gates with controlling decoder and negative power supply for a programmable logic device |
Sep. 1, 1998 |
| 5504439 |
I/O interface cell for use with optional pad |
Apr. 2, 1996 |
| 5187394 |
Configurable row decoder driver circuit |
Feb. 16, 1993 |
| 5056062 |
Method of operating an EPROM including delaying and boosting steps |
Oct. 8, 1991 |
| 4727267 |
Clocked buffer circuit |
Feb. 23, 1988 |
| 4700086 |
Consistent precharge circuit for cascode voltage switch logic |
Oct. 13, 1987 |
| 4678941 |
Boost word-line clock and decoder-driver circuits in semiconductor memories |
Jul. 7, 1987 |
| 4672240 |
Programmable redundancy circuit |
Jun. 9, 1987 |
| 4651031 |
Address decoder circuit |
Mar. 17, 1987 |
| 4631425 |
Logic gate circuit having P- and N- channel transistors coupled in parallel |
Dec. 23, 1986 |
| 4620116 |
Decoder circuit with setting function of an output level |
Oct. 28, 1986 |
| 4618784 |
High-performance, high-density CMOS decoder/driver circuit |
Oct. 21, 1986 |
| 4612462 |
Logic circuit having voltage booster |
Sep. 16, 1986 |
| 4611131 |
Low power decoder-driver circuit |
Sep. 9, 1986 |
| H97 |
Row-address-decoder-driver circuit |
Aug. 5, 1986 |
| 4563598 |
Low power consuming decoder circuit for a semiconductor memory device |
Jan. 7, 1986 |
| 4563599 |
Circuit for address transition detection |
Jan. 7, 1986 |
| 4554469 |
Static bootstrap semiconductor drive circuit |
Nov. 19, 1985 |
| 4542485 |
Semiconductor integrated circuit |
Sep. 17, 1985 |
| 4520463 |
Memory circuit |
May. 28, 1985 |
| 4509148 |
Semiconductor memory device |
Apr. 2, 1985 |
| 4500799 |
Bootstrap driver circuits for an MOS memory |
Feb. 19, 1985 |
| 4471240 |
Power-saving decoder for memories |
Sep. 11, 1984 |
| 4446386 |
MOS Decoder circuit using phase clocking for reducing the power consumption |
May. 1, 1984 |
| 4348596 |
Signal comparison circuit |
Sep. 7, 1982 |
| 4289982 |
Apparatus for programming a dynamic EPROM |
Sep. 15, 1981 |
| 4274147 |
Static read only memory |
Jun. 16, 1981 |
| 4103189 |
MOS Buffer circuit |
Jul. 25, 1978 |
| 4025799 |
Decoder structure for a folded logic array |
May. 24, 1977 |
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