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Class Information
Number: 326/106
Name: Electronic digital logic circuitry > Function of and, or, nand, nor, or not > Decoding > With field-effect transistor
Description: Subject matter wherein the logic circuit includes a unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electrical field applied to the semiconductor from a control electrode (gate).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7528631 |
Logic gate, scan driver and organic light emitting diode display using the same |
May. 5, 2009 |
| 7486113 |
Decoder circuit |
Feb. 3, 2009 |
| 7411424 |
Programmable logic function generator using non-volatile programmable memory switches |
Aug. 12, 2008 |
| 7245158 |
Circuit wiring layout in semiconductor memory device |
Jul. 17, 2007 |
| 7203243 |
Line driver with reduced power consumption |
Apr. 10, 2007 |
| 7199618 |
Logic circuit arrangement |
Apr. 3, 2007 |
| 7129755 |
High-fanin static multiplexer |
Oct. 31, 2006 |
| 7088139 |
Low power tri-level decoder circuit |
Aug. 8, 2006 |
| 7068069 |
Control circuit and reconfigurable logic block |
Jun. 27, 2006 |
| 7061275 |
Field programmable gate array |
Jun. 13, 2006 |
| 7049851 |
Decoder circuit |
May. 23, 2006 |
| 7042251 |
Multi-function differential logic gate |
May. 9, 2006 |
| 6998878 |
Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit |
Feb. 14, 2006 |
| 6963227 |
Apparatus and method for precharging and discharging a domino circuit |
Nov. 8, 2005 |
| 6954401 |
Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder |
Oct. 11, 2005 |
| 6949957 |
Command user interface with programmable decoder |
Sep. 27, 2005 |
| 6943589 |
Combination multiplexer and tristate driver circuit |
Sep. 13, 2005 |
| 6924670 |
Complementary input dynamic muxed-decoder |
Aug. 2, 2005 |
| 6859412 |
Circuit for controlling driver strengths of data and data strobe in semiconductor device |
Feb. 22, 2005 |
| 6809985 |
DRAM technology compatible processor/memory chips |
Oct. 26, 2004 |
| 6794906 |
Decoder scheme for making large size decoder |
Sep. 21, 2004 |
| 6756820 |
Optimized-delay multiplexer |
Jun. 29, 2004 |
| 6741519 |
DRAM technology compatible processor/memory chips |
May. 25, 2004 |
| 6696864 |
Logic circuit and its forming method |
Feb. 24, 2004 |
| 6657459 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them |
Dec. 2, 2003 |
| 6646949 |
Word line driver for dynamic random access memories |
Nov. 11, 2003 |
| 6624665 |
CMOS skewed static logic and method of synthesis |
Sep. 23, 2003 |
| 6618316 |
Pseudo-static single-ended cache cell |
Sep. 9, 2003 |
| 6600342 |
Column decoder of semiconductor memory device |
Jul. 29, 2003 |
| 6593776 |
Method and apparatus for low power domino decoding |
Jul. 15, 2003 |
| 6586970 |
Address decoder with pseudo and or pseudo nand gate |
Jul. 1, 2003 |
| 6552575 |
Word line testability improvement |
Apr. 22, 2003 |
| 6552566 |
Logic array circuits using silicon-on-insulator logic |
Apr. 22, 2003 |
| 6545892 |
Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
Apr. 8, 2003 |
| 6518792 |
Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling |
Feb. 11, 2003 |
| 6476644 |
Clocked logic gate circuit |
Nov. 5, 2002 |
| 6462580 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them |
Oct. 8, 2002 |
| 6459303 |
High speed programmable address decoder |
Oct. 1, 2002 |
| 6452856 |
DRAM technology compatible processor/memory chips |
Sep. 17, 2002 |
| 6426655 |
Row decoder with switched power supply |
Jul. 30, 2002 |
| 6404237 |
Boosted multiplexer transmission gate |
Jun. 11, 2002 |
| 6400183 |
Logic circuit and its forming method |
Jun. 4, 2002 |
| 6396306 |
Regenerative tie-high tie-low cell |
May. 28, 2002 |
| 6392445 |
Decoder element for producing an output signal having three different potentials |
May. 21, 2002 |
| 6388472 |
Word line decoder |
May. 14, 2002 |
| 6362658 |
Decoder for memories having optimized configuration |
Mar. 26, 2002 |
| 6323690 |
Logic circuit and its forming method |
Nov. 27, 2001 |
| 6323691 |
Logic circuit |
Nov. 27, 2001 |
| 6324117 |
Method of selecting a memory access line and an access line decoder for performing the same |
Nov. 27, 2001 |
| 6278297 |
Row decoder with switched power supply |
Aug. 21, 2001 |
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