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Class Information
Number: 326/101
Name: Electronic digital logic circuitry > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 4916333 |
Binary logic level electrical detector namely to prevent the detection of secret codes contained in a memory card |
Apr. 10, 1990 |
| 4914320 |
Speed-up circuit for NPN bipolar transistors |
Apr. 3, 1990 |
| 4904887 |
Semiconductor integrated circuit apparatus |
Feb. 27, 1990 |
| 4902916 |
Identification of defects in emitter-coupled logic circuits |
Feb. 20, 1990 |
| 4897705 |
Lateral bipolar transistor for logic circuit |
Jan. 30, 1990 |
| 4897560 |
Semiconductor integrated circuit with reduced power consumption |
Jan. 30, 1990 |
| 4896056 |
Semiconductor IC including circuit for preventing erroneous operation caused by power source noise |
Jan. 23, 1990 |
| 4866508 |
Integrated circuit packaging configuration for rapid customized design and unique test capability |
Sep. 12, 1989 |
| 4858175 |
Monolithic semi-custom IC having standard LSI sections and coupling gate array sections |
Aug. 15, 1989 |
| 4853560 |
Logic circuit and semiconductor integrated circuit device capable of operating by different power supplies |
Aug. 1, 1989 |
| 4835414 |
Flexible, reconfigurable terminal pin |
May. 30, 1989 |
| 4827368 |
Semiconductor integrated circuit device |
May. 2, 1989 |
| 4818895 |
Direct current sense lead |
Apr. 4, 1989 |
| 4814639 |
Super integration circuit device having a plurality of IC-chip equivalent regions formed on a single semiconductor substrate |
Mar. 21, 1989 |
| 4812678 |
Easily testable semiconductor LSI device |
Mar. 14, 1989 |
| 4812684 |
Multiphase clock distribution for VLSI chip |
Mar. 14, 1989 |
| 4789884 |
IIL circuit with PNP injector |
Dec. 6, 1988 |
| 4785202 |
Semiconductor integrated circuit device having an integrally formed bypass capacitor |
Nov. 15, 1988 |
| 4783605 |
Logic circuit made of biomaterials such as protein films |
Nov. 8, 1988 |
| 4782253 |
High speed MOS circuits |
Nov. 1, 1988 |
| 4780753 |
Semiconductor integrated circuit device |
Oct. 25, 1988 |
| 4771327 |
Master-slice integrated circuit having an improved arrangement of transistor elements for simplified wirings |
Sep. 13, 1988 |
| 4760349 |
CMOS analog standard cell arrays using linear transconductance elements |
Jul. 26, 1988 |
| 4760289 |
Two-level differential cascode current switch masterslice |
Jul. 26, 1988 |
| 4750027 |
Master slice semiconductor device |
Jun. 7, 1988 |
| 4748494 |
Lead arrangement for reducing voltage variation |
May. 31, 1988 |
| 4748488 |
Master-slice-type semiconductor integrated circuit device |
May. 31, 1988 |
| 4744076 |
Bus structure having constant electrical characteristics |
May. 10, 1988 |
| 4742019 |
Method for forming aligned interconnections between logic stages |
May. 3, 1988 |
| 4740720 |
Integrated injection logic output circuit |
Apr. 26, 1988 |
| 4733288 |
Gate-array chip |
Mar. 22, 1988 |
| 4716314 |
Integrated circuit |
Dec. 29, 1987 |
| 4714842 |
Integrated injection logic circuits |
Dec. 22, 1987 |
| 4701777 |
Gate array type semiconductor integrated circuit device |
Oct. 20, 1987 |
| 4694320 |
Semiconductor integrated circuit having multiple-layered connection |
Sep. 15, 1987 |
| 4692783 |
Gate array |
Sep. 8, 1987 |
| 4686394 |
ECL circuit with current-splitting network |
Aug. 11, 1987 |
| 4684831 |
Level shift circuit for interfacing between two different voltage levels using a current mirror circuit |
Aug. 4, 1987 |
| 4682055 |
CFET inverter having equal output signal rise and fall times by adjustment of the pull-up and pull-down transconductances |
Jul. 21, 1987 |
| 4682057 |
Circuit design technique to prevent current hogging when minimizing interconnect stripes by paralleling STL or ISL gate inputs |
Jul. 21, 1987 |
| 4672237 |
Logic circuit having delay time free from temperature affection |
Jun. 9, 1987 |
| 4642486 |
Decoder circuit using transistors or diodes of different characteristics |
Feb. 10, 1987 |
| 4629912 |
Schottky shunt integrated injection |
Dec. 16, 1986 |
| 4626889 |
Stacked differentially driven transmission line on integrated circuit |
Dec. 2, 1986 |
| 4626710 |
Low power logic circuit with storage charge control for fast switching |
Dec. 2, 1986 |
| 4612453 |
Integrated circuit device having a circuit means for detecting a disconnection of input signal line |
Sep. 16, 1986 |
| 4602270 |
Gate array with reduced isolation |
Jul. 22, 1986 |
| 4586169 |
Semiconductor memory circuit and large scale integrated circuit using the same |
Apr. 29, 1986 |
| 4583013 |
Oscillator signal detect circuit |
Apr. 15, 1986 |
| 4583111 |
Integrated circuit chip wiring arrangement providing reduced circuit inductance and controlled voltage gradients |
Apr. 15, 1986 |
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