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Class Information
Number: 326/101
Name: Electronic digital logic circuitry > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5233205 |
Quantum wave circuit |
Aug. 3, 1993 |
| 5191241 |
Programmable interconnect architecture |
Mar. 2, 1993 |
| 5175515 |
Signal routing technique for electronic systems |
Dec. 29, 1992 |
| 5172330 |
Clock buffers arranged in a peripheral region of the logic circuit area |
Dec. 15, 1992 |
| 5162675 |
Dual personal computer architecture peripheral adapter board and circuit |
Nov. 10, 1992 |
| 5155390 |
Programmable block architected heterogeneous integrated circuit |
Oct. 13, 1992 |
| 5153463 |
Programmable logic device having a reduced switching matrix |
Oct. 6, 1992 |
| 5140189 |
WSI decoder and patch circuit |
Aug. 18, 1992 |
| 5138197 |
Address decoder array composed of CMOS |
Aug. 11, 1992 |
| 5134314 |
Automatic pin circuitry shutoff for an integrated circuit |
Jul. 28, 1992 |
| 5132571 |
Programmable interconnect architecture having interconnects disposed above function modules |
Jul. 21, 1992 |
| 5124578 |
Receiver designed with large output drive and having unique input protection circuit |
Jun. 23, 1992 |
| 5122691 |
Integrated backplane interconnection architecture |
Jun. 16, 1992 |
| 5122693 |
Clock system implementing divided power supply wiring |
Jun. 16, 1992 |
| 5111073 |
Wafer-scale semiconductor device having fail-safe circuit |
May. 5, 1992 |
| 5093587 |
ECL bidirectional bus for use in a network with modules which employs high resistance interconnect technology between module |
Mar. 3, 1992 |
| 5087953 |
Flexible gate array system for combinatorial logic |
Feb. 11, 1992 |
| 5079442 |
Apparatus adaptable for use as a replacement output driver in a signal generating circuit |
Jan. 7, 1992 |
| 5079614 |
Gate array architecture with basic cell interleaved gate electrodes |
Jan. 7, 1992 |
| 5073729 |
Segmented routing architecture |
Dec. 17, 1991 |
| 5073703 |
Apparatus for encoding electrical identification devices by means of selectively fusible links |
Dec. 17, 1991 |
| 5070258 |
Integrated circuit having metal substrate used to provide electrical indication of operation mode of circuits |
Dec. 3, 1991 |
| 5068547 |
Process monitor circuit |
Nov. 26, 1991 |
| 5067003 |
Semicustom-made semiconductor integrated circuit having interface circuit selectively coupled to different voltage source |
Nov. 19, 1991 |
| 5066996 |
Channelless gate array with a shared bipolar transistor |
Nov. 19, 1991 |
| 5059831 |
Buffer circuit with an electrostatic protector |
Oct. 22, 1991 |
| 5055710 |
Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block |
Oct. 8, 1991 |
| 5049764 |
Active bypass for inhibiting high-frequency supply voltage variations in integrated circuits |
Sep. 17, 1991 |
| 5045725 |
Integrated standard cell including clock lines |
Sep. 3, 1991 |
| 5043597 |
Substrate bias generation circuit used in semiconductor integrated circuit |
Aug. 27, 1991 |
| 5031092 |
Microcomputer with high density ram in separate isolation well on single chip |
Jul. 9, 1991 |
| 5023482 |
ISL to TTL translator |
Jun. 11, 1991 |
| 5023689 |
Complementary integrated circuit device equipped with latch-up preventing means |
Jun. 11, 1991 |
| 5013935 |
CMOS level detctor circuit |
May. 7, 1991 |
| 5010260 |
Integrated circuit furnishing a segmented input circuit |
Apr. 23, 1991 |
| 5001487 |
Semiconductor integrated circuit device |
Mar. 19, 1991 |
| 4999687 |
Logic element and article comprising the element |
Mar. 12, 1991 |
| 4999520 |
High speed TTL buffer circuit which is resistive to the influence of alpha-rays |
Mar. 12, 1991 |
| 4992845 |
Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line |
Feb. 12, 1991 |
| 4984050 |
Gate-array type intergated circuit semiconductor device |
Jan. 8, 1991 |
| 4978867 |
Integrated circuit with on-chip voltage converter |
Dec. 18, 1990 |
| 4978869 |
ESD resistant latch circuit |
Dec. 18, 1990 |
| 4969018 |
Quantum-well logic using self-generated potentials |
Nov. 6, 1990 |
| 4967108 |
Differential-time-constant bandpass filter using the analog properties of digital circuits |
Oct. 30, 1990 |
| 4950927 |
Logic circuits for forming VLSI logic networks |
Aug. 21, 1990 |
| 4947058 |
TTL current sinking circuit with transient performance enhancement during output transition from high to low |
Aug. 7, 1990 |
| 4945257 |
Electrically settable resistance device |
Jul. 31, 1990 |
| 4943742 |
Schottky barrier diode clamp transistor |
Jul. 24, 1990 |
| 4942317 |
Master slice type semiconductor integrated circuit having 2 or more I/O cells per connection pad |
Jul. 17, 1990 |
| 4926066 |
Clock distribution circuit having minimal skew |
May. 15, 1990 |
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