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Class Information
Number: 326/101
Name: Electronic digital logic circuitry > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6218855 |
Datapath global routing using flexible pins for side exiting buses |
Apr. 17, 2001 |
| 6216256 |
Semiconductor integrated circuit and method of designing the same |
Apr. 10, 2001 |
| 6211703 |
Signal transmission system |
Apr. 3, 2001 |
| 6201411 |
Programmable integrated circuit having metal plate capacitors that provide local switching energy |
Mar. 13, 2001 |
| 6191609 |
Combination of global clock and localized clocks |
Feb. 20, 2001 |
| 6184702 |
Crosstalk prevention circuit |
Feb. 6, 2001 |
| 6184711 |
Low impact signal buffering in integrated circuits |
Feb. 6, 2001 |
| 6172526 |
Input/output interface including an output buffer circuit and depletion type field effect transistor |
Jan. 9, 2001 |
| 6170079 |
Power supply circuit diagram design system |
Jan. 2, 2001 |
| 6169418 |
Efficient routing from multiple sources to embedded DRAM and other large circuit blocks |
Jan. 2, 2001 |
| 6157213 |
Layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single chip |
Dec. 5, 2000 |
| 6150840 |
Programmable reticle stitching |
Nov. 21, 2000 |
| 6150877 |
Semiconductor device with improved circuit interconnection |
Nov. 21, 2000 |
| 6144224 |
Clock distribution network with dual wire routing |
Nov. 7, 2000 |
| 6140883 |
Tunable, energy efficient clocking scheme |
Oct. 31, 2000 |
| 6137316 |
Integrated circuit with improved off chip drivers |
Oct. 24, 2000 |
| 6133750 |
Combination of global clock and localized clocks |
Oct. 17, 2000 |
| 6133752 |
Semiconductor integrated circuit having tri-state logic gate circuit |
Oct. 17, 2000 |
| 6130551 |
Synthesis-friendly FPGA architecture with variable length and variable timing interconnect |
Oct. 10, 2000 |
| 6127845 |
Field programmable gate array having internal logic transistors with two different gate insulator thicknesses |
Oct. 3, 2000 |
| 6127844 |
PCI-compatible programmable logic devices |
Oct. 3, 2000 |
| 6127851 |
Circuit and method for differentiating multiple modules |
Oct. 3, 2000 |
| 6124729 |
Field programmable logic arrays with vertical transistors |
Sep. 26, 2000 |
| 6114877 |
Timing circuit utilizing a clock tree as a delay device |
Sep. 5, 2000 |
| 6114878 |
Circuit for contact pad isolation |
Sep. 5, 2000 |
| RE36839 |
Method and apparatus for reducing power consumption in digital electronic circuits |
Aug. 29, 2000 |
| 6107826 |
Interconnect structure for FPGA with configurable delay locked loop |
Aug. 22, 2000 |
| 6083274 |
Integrated structure layout and layout of interconnections for an integrated circuit chip |
Jul. 4, 2000 |
| 6066959 |
Logic array having multi-level logic planes |
May. 23, 2000 |
| 6060911 |
Circuit arrangement with at least four transistors, and method for the manufacture thereof |
May. 9, 2000 |
| 6060901 |
Multiple function electrical circuit configurable by orientation of an integrated circuit chip |
May. 9, 2000 |
| 6057708 |
Field programmable gate array having a dedicated internal bus system |
May. 2, 2000 |
| 6054872 |
Semiconductor integrated circuit with mixed gate array and standard cell |
Apr. 25, 2000 |
| 6037805 |
Integrated circuit device having small amplitude signal transmission |
Mar. 14, 2000 |
| 6034539 |
Bonding-option architecture for integrated circuitry |
Mar. 7, 2000 |
| 6025740 |
Clock feeding circuit and method for adjusting clock skew |
Feb. 15, 2000 |
| 6003107 |
Circuitry for providing external access to signals that are internal to an integrated circuit chip package |
Dec. 14, 1999 |
| 5994924 |
Clock distribution network with dual wire routing |
Nov. 30, 1999 |
| 5986477 |
Method and system for providing an interconnect layout to reduce delays in logic circuits |
Nov. 16, 1999 |
| 5982194 |
Arithmetic and logic function circuits optimized for datapath layout |
Nov. 9, 1999 |
| 5977794 |
Logic array having interleaved logic planes |
Nov. 2, 1999 |
| 5969544 |
Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit |
Oct. 19, 1999 |
| 5945846 |
Clock driver circuit in a centrally located macro cell layout region |
Aug. 31, 1999 |
| 5923188 |
Clock signal distribution circuit of tree structure with minimized skew |
Jul. 13, 1999 |
| 5872716 |
Semiconductor integrated logic circuit device using a pass transistor |
Feb. 16, 1999 |
| 5867040 |
Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor |
Feb. 2, 1999 |
| 5861764 |
Clock skew reduction using spider clock trace routing |
Jan. 19, 1999 |
| 5818263 |
Method and apparatus for locating and improving race conditions in VLSI integrated circuits |
Oct. 6, 1998 |
| 5764084 |
Time multiplexed ratioed logic |
Jun. 9, 1998 |
| 5757208 |
Programmable array and method for routing power busses therein |
May. 26, 1998 |
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