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Class Information
Number: 326/101
Name: Electronic digital logic circuitry > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6434646 |
Signal distribution system and method based on bus arrangement |
Aug. 13, 2002 |
| 6429680 |
Pin programmable reference |
Aug. 6, 2002 |
| 6430735 |
Semiconductor integrated circuit having thereon on-chip capacitors |
Aug. 6, 2002 |
| 6426645 |
Semiconductor device that fixes a potential on an input signal wiring |
Jul. 30, 2002 |
| 6426650 |
Integrated circuit with metal programmable logic having enhanced reliability |
Jul. 30, 2002 |
| 6417695 |
Antifuse reroute of dies |
Jul. 9, 2002 |
| 6414542 |
Integrated circuit with relative sense inversion of signals along adjacent parallel signal paths |
Jul. 2, 2002 |
| 6414518 |
Circuitry for a low internal voltage integrated circuit |
Jul. 2, 2002 |
| 6411124 |
Programmable logic device logic modules with shift register capabilities |
Jun. 25, 2002 |
| 6407586 |
Fusible link configuration in integrated circuits |
Jun. 18, 2002 |
| 6404226 |
Integrated circuit with standard cell logic and spare gates |
Jun. 11, 2002 |
| 6401232 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Jun. 4, 2002 |
| 6400182 |
Semiconductor integrated circuit device and method of laying out clock driver used in the semiconductor integrated circuit device |
Jun. 4, 2002 |
| 6397375 |
Method for managing metal resources for over-the-block routing in integrated circuits |
May. 28, 2002 |
| 6396300 |
Circuit and method for contact pad isolation |
May. 28, 2002 |
| 6388473 |
Logic product circuit |
May. 14, 2002 |
| 6381732 |
FPGA customizable to accept selected macros |
Apr. 30, 2002 |
| 6380765 |
Double pass transistor logic with vertical gate transistors |
Apr. 30, 2002 |
| 6377070 |
In-service programmable logic arrays with ultra thin vertical body transistors |
Apr. 23, 2002 |
| 6373288 |
Method of implementing clock trees in synchronous digital electronic circuits, and a programmable delay buffer stage therefor |
Apr. 16, 2002 |
| 6366131 |
System and method for increasing a drive signal and decreasing a pin count |
Apr. 2, 2002 |
| 6362651 |
Method for fabricating PLDs including multiple discrete devices formed on a single chip |
Mar. 26, 2002 |
| 6362644 |
Programmable termination for integrated circuits |
Mar. 26, 2002 |
| 6356118 |
Semiconductor integrated circuit device |
Mar. 12, 2002 |
| 6356116 |
Apparatus and method for low skew clock buffer circuit |
Mar. 12, 2002 |
| 6353352 |
Clock tree topology |
Mar. 5, 2002 |
| 6346826 |
Programmable gate array device |
Feb. 12, 2002 |
| 6337579 |
Multichip semiconductor device |
Jan. 8, 2002 |
| 6335640 |
Semiconductor integrated circuit device with its layout designed by the cell base method |
Jan. 1, 2002 |
| 6335635 |
Programmable reticle stitching |
Jan. 1, 2002 |
| RE37475 |
Logic synthesis method and semiconductor integrated circuit |
Dec. 18, 2001 |
| 6329845 |
Logic gate cell |
Dec. 11, 2001 |
| 6323679 |
Flexible programmable logic module |
Nov. 27, 2001 |
| 6323689 |
Semiconductor integrated circuit including output buffer circuit having high resistance to electro-static discharge |
Nov. 27, 2001 |
| 6317862 |
Modular preamplifier head circuit layout |
Nov. 13, 2001 |
| 6313665 |
Semiconductor integrated circuit |
Nov. 6, 2001 |
| 6307238 |
Methods of forming field effect transistors and field effect transistor circuitry |
Oct. 23, 2001 |
| 6297668 |
Serial device compaction for improving integrated circuit layouts |
Oct. 2, 2001 |
| 6292024 |
Integrated circuit with a serpentine conductor track for circuit selection |
Sep. 18, 2001 |
| 6292015 |
Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation |
Sep. 18, 2001 |
| 6285208 |
Activation speed of signal wiring line in semiconductor integrated circuit |
Sep. 4, 2001 |
| 6281704 |
High-performance interconnect |
Aug. 28, 2001 |
| 6271681 |
PCI-compatible programmable logic devices |
Aug. 7, 2001 |
| 6260184 |
Design of an integrated circuit by selectively reducing or maintaining power lines of the device |
Jul. 10, 2001 |
| 6255845 |
Efficient use of spare gates for post-silicon debug and enhancements |
Jul. 3, 2001 |
| 6239615 |
High-performance interconnect |
May. 29, 2001 |
| 6236228 |
Structure and method of repair of integrated circuits |
May. 22, 2001 |
| 6225821 |
Package migration for related programmable logic devices |
May. 1, 2001 |
| 6218866 |
Semiconductor device for prevention of a floating gate condition on an input node of a MOS logic circuit and a method for its manufacture |
Apr. 17, 2001 |
| 6218865 |
Semiconductor device having function blocks with obliquely arranged signal terminals connected through two-dimensionally extensible signal lines |
Apr. 17, 2001 |
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