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Class Information
Number: 326/101
Name: Electronic digital logic circuitry > Significant integrated structure, layout, or layout interconnections
Description: Subject matter including an arrangement of components fabricated in a semiconductor material or integrated circuit chip with significant design emphasis on the topological arrangement of the components and their circuit connectors.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6950891 |
Signal routing between a memory control unit and a memory device |
Sep. 27, 2005 |
| 6943584 |
Programmable semiconductor device including universal logic modules coping with as many user inverters |
Sep. 13, 2005 |
| 6930511 |
Array of programmable cells with customized interconnections |
Aug. 16, 2005 |
| 6924666 |
Integrated logic circuit and hierarchical design method thereof |
Aug. 2, 2005 |
| 6917998 |
Reusable complex multi-bus system hardware prototype system |
Jul. 12, 2005 |
| 6898777 |
Block level routing architecture in a field programmable gate array |
May. 24, 2005 |
| 6892363 |
Correction of width violations of dummy geometries |
May. 10, 2005 |
| 6879185 |
Low power clock distribution scheme |
Apr. 12, 2005 |
| 6880144 |
High speed low power bitline |
Apr. 12, 2005 |
| 6873185 |
Logic array devices having complex macro-cell architecture and methods facilitating use of same |
Mar. 29, 2005 |
| 6864558 |
Layout technique for C3MOS inductive broadbanding |
Mar. 8, 2005 |
| 6864712 |
Hardening logic devices |
Mar. 8, 2005 |
| 6864716 |
Reconfigurable memory architecture |
Mar. 8, 2005 |
| 6831479 |
Circuit for reducing pin count of a semiconductor chip and method for configuring the chip |
Dec. 14, 2004 |
| 6828852 |
Active pulsed scheme for driving long interconnects |
Dec. 7, 2004 |
| 6828824 |
Heterogeneous interconnection architecture for programmable logic devices |
Dec. 7, 2004 |
| 6825687 |
Selective cooling of an integrated circuit for minimizing power loss |
Nov. 30, 2004 |
| 6825690 |
Clock tree network in a field programmable gate array |
Nov. 30, 2004 |
| 6822887 |
Semiconductor circuit device with mitigated load on interconnection line |
Nov. 23, 2004 |
| 6819136 |
Customizable and programmable cell array |
Nov. 16, 2004 |
| 6815982 |
Electrical or electronic circuit arrangement and associated method |
Nov. 9, 2004 |
| 6812742 |
Electronic device |
Nov. 2, 2004 |
| 6810511 |
Method of designing active region pattern with shift dummy pattern |
Oct. 26, 2004 |
| 6810512 |
Integrated circuit with layout matched high speed lines |
Oct. 26, 2004 |
| 6806738 |
Semiconductor circuit device capable of high speed decoding |
Oct. 19, 2004 |
| 6794904 |
Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation |
Sep. 21, 2004 |
| 6783372 |
Apparatus for connecting semiconductor modules |
Aug. 31, 2004 |
| 6782521 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Aug. 24, 2004 |
| 6768346 |
Signal transmission system |
Jul. 27, 2004 |
| 6762619 |
Semiconductor integrated device and electronic equipment |
Jul. 13, 2004 |
| 6759698 |
Semiconductor integrated circuit |
Jul. 6, 2004 |
| 6757872 |
Command user interface with programmable decoder |
Jun. 29, 2004 |
| 6756811 |
Customizable and programmable cell array |
Jun. 29, 2004 |
| 6753702 |
Semiconductor integrated circuit and its layout method |
Jun. 22, 2004 |
| 6747478 |
Field programmable gate array with convertibility to application specific integrated circuit |
Jun. 8, 2004 |
| 6744273 |
Semiconductor device capable of reducing noise to signal line |
Jun. 1, 2004 |
| 6710625 |
Semiconductor integrated circuit having a gate array structure |
Mar. 23, 2004 |
| 6710991 |
Electrostatic-breakdown-preventive and protective circuit for semiconductor-device |
Mar. 23, 2004 |
| 6703868 |
Methods, apparatus, and systems for reducing interference on nearby conductors |
Mar. 9, 2004 |
| 6703869 |
Method and apparatus for low latency distribution of logic signals |
Mar. 9, 2004 |
| 6700402 |
Output control circuit and output control method |
Mar. 2, 2004 |
| 6696863 |
Clock signal distribution circuit |
Feb. 24, 2004 |
| 6693801 |
Electronic device |
Feb. 17, 2004 |
| 6693453 |
Re-programmable logic array |
Feb. 17, 2004 |
| 6690206 |
Semiconductor integrated circuit device |
Feb. 10, 2004 |
| 6686766 |
Technique to reduce reflections and ringing on CMOS interconnections |
Feb. 3, 2004 |
| 6686768 |
Electrically-programmable interconnect architecture for easily-configurable stacked circuit arrangements |
Feb. 3, 2004 |
| 6678877 |
Creating a PC board (PCB) layout for a circuit in which the components of the circuit are placed in the determined PCB landing areas |
Jan. 13, 2004 |
| 6677781 |
Semiconductor integrated circuit device |
Jan. 13, 2004 |
| 6674307 |
General-purpose logic module and cell using the same |
Jan. 6, 2004 |
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